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41. 发明申请

WO2008064262A2 IMPROVED FREQUENCY CHANGER CIRCUITS 审中-公开
标题翻译：改进的变频器电路
公开(公告)号：WO2008064262A2
公开(公告)日：2008-05-29
申请号：PCT/US2007/085296
申请日：2007-11-20
申请人： QUALCOMM INCORPORATED , FILIPOVIC, Daniel, F. , KANG, Inyup
发明人： FILIPOVIC, Daniel, F. , KANG, Inyup
CPC分类号： H04B15/00 , H04B1/109
摘要： In accordance with one aspect of the disclosure, apparatus are provided. A filter is provided to receive from an antenna a receive signal of a given type and a low noise amplifier is provided to amplify the received signal. A translator down translates the receive signal carried at a radio frequency to be carried at an intermediate frequency. An I/Q channel separator is provided to separate the receive signal carried at the intermediate frequency into an analog in-phase (I) signal in an I channel and an analog quadrature-phase (Q) in a Q channel. An analog-to-digital (A/D) converter is provided to respectively convert the I signal and the Q signal to digital domain representations of the I signal and the Q signal. An intermodulation (IM) distortion avoider is provided to avoid IM distortion in the receive signal. The IM distortion avoider includes a carrier frequency exchanger to exchange an IM carrier frequency of IM distortion contained in the receive signal with a carrier frequency of the receive signal.
摘要翻译：根据本公开的一个方面，提供了一种装置。提供滤波器以从天线接收给定类型的接收信号，并且提供低噪声放大器来放大接收到的信号。翻译器将在射频下携带的接收信号转换为中频。提供I / Q信道分离器以将在中频处承载的接收信号分离成I信道中的模拟同相（I）信号和Q信道中的模拟正交相位（Q）。提供模数（A / D）转换器以分别将I信号和Q信号转换为I信号和Q信号的数字域表示。提供互调（IM）失真避免器以避免接收信号中的IM失真。 IM失真避免器包括载波频率交换器，以将接收信号中包含的IM失真的IM载波频率与接收信号的载波频率进行交换。

42. 发明申请

WO2008061167A1 ITERATIVE DETECTION AND CANCELLATION FOR WIRELESS COMMUNICATION 审中-公开
标题翻译：无线通信的迭代检测和取消
公开(公告)号：WO2008061167A1
公开(公告)日：2008-05-22
申请号：PCT/US2007/084750
申请日：2007-11-15
申请人： QUALCOMM INCORPORATED , SHIM, Byonghyo , ABRISHAMKAR, Farrokh , KANG, Inyup
发明人： SHIM, Byonghyo , ABRISHAMKAR, Farrokh , KANG, Inyup
IPC分类号： H04B1/707
CPC分类号： H04B1/71072 , H04B1/71055 , H04B1/71075 , H04B1/7115 , H04B2201/70702
摘要： Techniques for recovering a desired transmission in the presence of interfering transmissions are described. For iterative detection and cancellation, multiple groups of code channels are formed for a plurality of code channels for at least one sector. Processing is performed for the multiple groups of code channels in multiple iterations. For each iteration, data detection and signal cancellation are performed for the multiple groups of code channels in multiple stages, e.g., in a sequential order starting with the strongest group to the weakest group. Each stage of each iteration may perform data detection, signal reconstruction, and signal cancellation. Each stage of each iteration may also perform equalization, data detection, signal reconstruction, and signal cancellation.
摘要翻译：描述了在存在干扰传输的情况下恢复所需传输的技术。对于迭代检测和消除，针对至少一个扇区的多个代码信道形成多组代码信道组。在多个迭代中针对多组代码信道执行处理。对于每个迭代，对于多个阶段的多组代码信道执行数据检测和信号消除，例如以从最强组到最弱组的顺序顺序执行。每个迭代的每个阶段都可以执行数据检测，信号重建和信号消除。每个迭代的每个阶段也可以执行均衡，数据检测，信号重建和信号消除。

43. 发明申请

WO2008061123A2 SUCCESSIVE EQUALIZATION AND CANCELLATION AND SUCCESSIVE MINI MULTI-USER DETECTION FOR WIRELESS COMMUNICATION 审中-公开
标题翻译：无线通信的均衡和取消和成功的微型多用户检测
公开(公告)号：WO2008061123A2
公开(公告)日：2008-05-22
申请号：PCT/US2007/084641
申请日：2007-11-14
申请人： QUALCOMM Incorporated , SHIM, Byonghyo , KANG, Inyup , ABRISHAMKAR, Farrokh , SAMBHWANI, Sharad, Deepak
发明人： SHIM, Byonghyo , KANG, Inyup , ABRISHAMKAR, Farrokh , SAMBHWANI, Sharad, Deepak
IPC分类号： H04L25/03
CPC分类号： H04L25/03006 , H04B1/71072 , H04L2025/03617
摘要： Techniques for recovering a desired transmission in the presence of interfering transmissions are described. For successive equalization and cancellation (SEC), equalization is performed on a received signal to obtain an equalized signal for a first set of code channels. The first set may include all code channels for one sector, a subset of all code channels for one sector, multiple code channels for multiple sectors, etc. Data detection is then performed on the equalized signal to obtain a detected signal for the first set of code channels. A signal for the first set of code channels is reconstructed based on the detected signal. The reconstructed signal for the first set of code channels is then canceled from the received signal. Equalization, data detection, reconstruction, and cancellation are performed for at least one additional set of code channels in similar manner.
摘要翻译：描述了在存在干扰传输的情况下恢复所需传输的技术。对于连续均衡和消除（SEC），对接收到的信号执行均衡以获得第一组码信道的均衡信号。第一组可以包括一个扇区的所有码信道，一个扇区的所有码信道的子集，多个扇区的多个码信道等。然后，对均衡信号执行数据检测，以获得第一组的第一组的检测信号代码渠道基于检测到的信号重建用于第一组码信道的信号。然后，从接收到的信号中取消用于第一组码信道的重建信号。对于至少一个附加的代码信道集合以类似的方式执行均衡，数据检测，重建和消除。

44. 发明申请

WO2005034546A1 POWER COLLAPSE FOR A WIRELESS TERMINAL 审中-公开
标题翻译：无线终端的功率收敛
公开(公告)号：WO2005034546A1
公开(公告)日：2005-04-14
申请号：PCT/US2004/028579
申请日：2004-09-01
申请人： QUALCOMM Incorporated , KANG, Inyup , ETHIRAJAN, Karthikeyan
发明人： KANG, Inyup , ETHIRAJAN, Karthikeyan
IPC分类号： H04Q7/32
CPC分类号： H04W52/028 , Y02D70/122 , Y02D70/1242 , Y02D70/144
摘要： An integrated circuit for a modem processor includes processing units that are partitioned into "always-on" and "collapsible" power domains. An always-on power domain is powered on at all times. A collapsible power domain can be powered off if the processing units in the power domain are not needed. A power control unit within an always-on power domain powers down the collapsible power domains after going into sleep and powers up these domains after waking up from sleep. Tasks for powering down the collapsible power domains may include (1) saving pertinent hardware registers for these power domains, (2) freezing output pins of the IC to minimally disturb external units, (3) clamping input pins of the collapsed power domains, (4) powering down a main oscillator and disabling the oscillator clock, and so on. Complementary tasks are performed for powering up the collapsed power domains.
摘要翻译：用于调制解调器处理器的集成电路包括被划分为“永远在线”和“可折叠”电力域的处理单元。永远在线的电源域始终打开。如果不需要电源域中的处理单元，则可以关闭可折叠电源域。永远在线的电源域内的电源控制单元在睡眠后唤醒可折叠的电源域，并在从睡眠中唤醒之后启动这些域。关闭可折叠电源域的任务可能包括（1）保存这些电源域的相关硬件寄存器，（2）冻结IC的输出引脚以最小限度地干扰外部单元，（3）钳位崩溃的电源域的输入引脚（ 4）关闭主振荡器并禁用振荡器时钟，等等。执行补充任务以加电折叠的电源域。

45. 发明申请

WO2003088606A2 DIRECT CURRENT OFFSET CANCELLATION FOR MOBILE STATION MODEMS USING DIRECT CONVERSION 审中-公开
标题翻译：使用直接转换的移动站模式的直接电流消除
公开(公告)号：WO2003088606A2
公开(公告)日：2003-10-23
申请号：PCT/US2003/011070
申请日：2003-04-09
申请人： QUALCOMM INCORPORATED
发明人： HOLENSTEIN, Christian , KANG, Inyup , SEVERSON, Matthew
IPC分类号： H04L25/06
CPC分类号： H04L25/061 , H04B1/30
摘要： A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.
摘要翻译：一种具有直接转换结构的移动台调制解调器的DC偏移消除系统和方法。本发明是快速获取DC偏移消除块，其提供快速和准确的DC偏移估计和消除技术以支持直接转换架构。快速获取DC偏移消除块结合了四种机制，通过增加高通环路带宽和调整基带上的直流偏移电平，快速获取和消除上电，温度变化，接收机频率变化和增益设置变化后的直流偏移估计。在大部分去除DC偏移之后，降低高通环路带宽以微调先前的估计，并消除由于接收机自混合产物引起的DC偏移的任何小的变化。

46. 发明申请

WO2003065610A3 BUFFER-BASED GPS AND CDMA PILOT SEARCHER 审中-公开
公开(公告)号：WO2003065610A3
公开(公告)日：2003-08-07
申请号：PCT/US2003/002912
申请日：2003-01-31
申请人： QUALCOMM INCORPORATED
发明人： KANG, Inyup , PATRICK, Christopher , MEAGHER, Bruce, R. , PATEL, Shimman , LI, Tao , CHEUNG, Joseph , SRINAVAS, Pillappakkam , FOERSTER, Gregory, B. , VARADARAJAN, Srinivas , WEI, Jian
IPC分类号： H04B1/707
摘要： A pilot searcher for CDMA and GPS signals. In one aspect, the searcher is operated in conjunction with a sample buffer in a "real-time" or "off-line" mode. The writing/reading of samples to/from the buffer may be performed in a TDM manner via a common port, and samples may be decimated and packed prior to storing in the buffer. In another aspect, the overall search for pilots is partitioned into a number of tasks, with each task corresponding to a search over a given sample segment and based on a particular set of parameter values. The tasks may be stored in a queue and performed one at a time based on their order in the queue. Prior to performing a new task, the parameter values for that task is downloaded to a set of configuration registers. The parameters may be ordered and linked such that only new values are downloaded.

47. 发明申请

WO2002099990A1 METHOD AND APPARATUS FOR SEARCHING TIME-DIVISION MULTIPLEXED SYNCHRONIZATION SEQUENCES 审中-公开
标题翻译：搜索时分多址同步序列的方法和装置
公开(公告)号：WO2002099990A1
公开(公告)日：2002-12-12
申请号：PCT/US2002/017043
申请日：2002-05-31
申请人： QUALCOMM INCORPORATED
发明人： KANG, Inyup , Li, Tao
IPC分类号： H04B1/707
CPC分类号： H04B1/70752 , H04B1/7077
摘要： In a real-time mode, a clock signal of a searcher architecture is disabled between synchronization sequence bursts. In a sample storage or asynchronous mode, portions of stored signals do not belong to any hypothesis to be tested (e.g. portions that occur between synchronization signal bursts) are not loaded into the searcher delay chain.
摘要翻译：在实时模式中，搜索器架构的时钟信号在同步序列突发之间被禁用。在样本存储或异步模式中，存储的信号的部分不属于要测试的任何假设（例如，在同步信号突发之间发生的部分）未被加载到搜索器延迟链中。

48. 发明授权

EP2165334B1 CONCURRENT MULTIPLE-DIMENSION WORD-ADDRESSABLE MEMORY ARCHITECTURE 有权
标题翻译：同时与多个维度WORDADRESSIERBARE存储器架构
公开(公告)号：EP2165334B1
公开(公告)日：2014-04-23
申请号：EP08772064.5
申请日：2008-06-26
申请人： QUALCOMM Incorporated
发明人： CHEN, Chih-Tung , KANG, Inyup , CHAIYAKUL, Viraphol
IPC分类号： G11C8/16 , G06F12/02
CPC分类号： G11C8/10 , G06F12/0207 , G11C8/16 , H03M13/2707 , H03M13/2764

49. 发明公开

EP2165334A1 CONCURRENT MULTIPLE-DIMENSION WORD-ADDRESSABLE MEMORY ARCHITECTURE 有权
标题翻译：同时与多个维度WORDADRESSIERBARE存储器架构
公开(公告)号：EP2165334A1
公开(公告)日：2010-03-24
申请号：EP08772064.5
申请日：2008-06-26
申请人： QUALCOMM Incorporated
发明人： CHEN, Chih-Tung , KANG, Inyup , CHAIYAKUL, Viraphol
IPC分类号： G11C8/16 , G06F12/02
CPC分类号： G11C8/10 , G06F12/0207 , G11C8/16 , H03M13/2707 , H03M13/2764
摘要： An N-dimension addressable memory is disclosed. The memory includes an Ndimension array of bit cells and logic configured to address each bit cell using NDimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.

50. 发明授权

EP1336257B1 SYSTEM AND METHOD OF DESKEW BUFFERING CDMA SIGNALS 有权
标题翻译：系统和方法CDMA偏移校正缓存信号
公开(公告)号：EP1336257B1
公开(公告)日：2009-04-01
申请号：EP01997903.8
申请日：2001-11-16
申请人： QUALCOMM INCORPORATED
发明人： KANG, Inyup
IPC分类号： H04B1/707
CPC分类号： H04B1/7117 , H04B1/712 , H04B2201/70703 , H04B2201/70707
摘要： A deskew buffer 410 arrangement in a CDMA receiver allows for accurate combining of symbols from a plurality of demodulator fingers, 402 and 404, without any symbol losses when the data rate is changed. A single deskew buffer 410 is coupled to a plurality of demodulator fingers, each of which demodulate an assigned multipath. The symbols are written into the deskew buffer 410 according to a PN count value modified by a predetermined bit pattern. The demodulator finger is able to demodulate a plurality of data rates corresponding to a plurality of Walsh lengths. Each data rate is assigned a corresponding deskew index. The PN count value represents an address within the deskew buffer 410. The lower bits of the PN count, where the number of bits corresponds to the deskew index, are truncated and replaced with the predetermined bit pattern. In one embodiment the predetermined bit pattern is all ones.

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