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41. 发明授权

US07106627B2 Nonvolatile semiconductor memory device with redundancy and security information circuitry 有权
标题翻译：具有冗余和安全信息电路的非易失性半导体存储器件
公开(公告)号：US07106627B2
公开(公告)日：2006-09-12
申请号：US11194716
申请日：2005-08-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/22 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has memory elements selected by an address signal. The second storage area has memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区域具有由地址信号选择的存储元件。第二存储区域具有通过控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

42. 发明申请

US20050265092A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050265092A1
公开(公告)日：2005-12-01
申请号：US11194716
申请日：2005-08-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G06F12/16 , G11C7/00 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/06 , G11C29/42
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

43. 发明授权

US06657891B1 Semiconductor memory device for storing multivalued data 有权
标题翻译：用于存储多值数据的半导体存储器件
公开(公告)号：US06657891B1
公开(公告)日：2003-12-02
申请号：US10358643
申请日：2003-02-04
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C2211/5642 , G11C2211/5648
摘要： Before the next data is stored into a first memory cell in which i bits of data have been stored, i or less bits of data are written into cells adjacent to the first memory cell beforehand. The writing of i or less bits of data is done using a threshold voltage lower than the original threshold voltage (or the actual threshold voltage in storing i bits of data). After the adjacent cells have been written into, writing is done to raise the threshold voltage of the first memory cell.
摘要翻译：在下一个数据被存储到已经存储了i个比特数据的第一存储单元中之前，预先将I或更少的数据位写入与第一存储单元相邻的单元。使用低于原始阈值电压（或存储i位数据的实际阈值电压）的阈值电压来完成I或更少数据位的写入。在相邻单元被写入之后，进行写入以提高第一存储单元的阈值电压。

44. 发明授权

US06650578B2 Semiconductor storage device and setting method thereof 有权
标题翻译：半导体存储装置及其设定方法
公开(公告)号：US06650578B2
公开(公告)日：2003-11-18
申请号：US10229147
申请日：2002-08-28
申请人： Masatsugu Kojima , Tomoharu Tanaka , Noboru Shibata
发明人： Masatsugu Kojima , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/808
摘要： A semiconductor storage device includes a main memory cell array and a redundancy memory cell array. The redundancy memory cell array is set to selectively have a replacing area replacing a defective memory cell in the main memory cell array, and a non-replacing area other than the replacing area. Memory cells in the main memory cell array and the redundancy memory cell array are selected and driven by a memory selection circuit. A control section for controlling the memory selection circuit is set to assign main memory addresses to memory cells in the non-replacing area, and use these memory cells as an expansion area of the main memory cell array.
摘要翻译：半导体存储装置包括主存储单元阵列和冗余存储单元阵列。冗余存储单元阵列被设置为选择性地具有替换主存储单元阵列中的有缺陷存储单元的替换区域和替换区域以外的非替换区域。主存储单元阵列和冗余存储单元阵列中的存储单元由存储器选择电路选择和驱动。设置用于控制存储器选择电路的控制部分，以将主存储器地址分配给非替代区域中的存储单元，并将这些存储单元用作主存储单元阵列的扩展区域。

45. 发明授权

US06377485B1 Multi-value semiconductor memory device and reading method thereof 有权
标题翻译：多值半导体存储器件及其读取方法
公开(公告)号：US06377485B1
公开(公告)日：2002-04-23
申请号：US09721385
申请日：2000-11-22
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C1634
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C2211/5621 , G11C2211/5642
摘要： For a verify operation using potential Vbi′, the data of a memory cell is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi′. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.
摘要翻译：对于使用电位Vbi'的验证操作，通过使用电位Vai + 1预先读取存储单元的数据，并将存储单元的状态存储在锁存电路中。然后，通过使用电位Vbi'进行验证/读取操作。如果单元的状态高于Ai + 1，则验证/读取操作的结果被强制降低到低水平。因此，只需要两个锁存电路来存储n位数据，包括一个用于存储要写入的数据的数据，一个用于在小区的状态高于Ai + 1时预先读取，并且存储初步阅读。

46. 发明授权

US08619468B2 Semiconductor memory device for storing multivalued data 有权
公开(公告)号：US08619468B2
公开(公告)日：2013-12-31
申请号：US13648778
申请日：2012-10-10
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.

47. 发明授权

US08385130B2 Semiconductor memory device which stores plural data in a cell 有权
公开(公告)号：US08385130B2
公开(公告)日：2013-02-26
申请号：US13413779
申请日：2012-03-07
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k

48. 发明授权

US08310871B2 Semiconductor memory device for storing multivalued data 有权
标题翻译：用于存储多值数据的半导体存储器件
公开(公告)号：US08310871B2
公开(公告)日：2012-11-13
申请号：US13158508
申请日：2011-06-13
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
摘要翻译：数据存储电路以一一对应的方式连接到位线。写入电路将第一页上的数据写入由字线同时选择的多个5个第一存储单元。此后，写电路将第二页上的数据写入多个第一存储单元。然后，写入电路将第一和第二页上的数据写入与位线方向上的第一存储单元相邻的第二存储单元。

49. 发明申请

US20120224422A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120224422A1
公开(公告)日：2012-09-06
申请号：US13471143
申请日：2012-05-14
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

50. 发明申请

US20110116315A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110116315A1
公开(公告)日：2011-05-19
申请号：US13012030
申请日：2011-01-24
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

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