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41. 发明授权

US09013339B2 Track and hold architecture with tunable bandwidth 有权
标题翻译：跟踪和保持具有可调带宽的架构
公开(公告)号：US09013339B2
公开(公告)日：2015-04-21
申请号：US13551950
申请日：2012-07-18
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03M1/00 , H03M1/08 , H03M1/12
CPC分类号： H03M1/08 , H03M1/1215
摘要： To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.
摘要翻译：到目前为止，时间交织（TI）模数转换器（ADC）中的带宽不匹配已被大大忽略，因为通过数字后处理（即有限脉冲响应滤波器）执行带宽不匹配的补偿。然而，数字后处理的滞后在高速系统中是禁止的，表明需要盲目错配补偿。即使使用盲带宽失配估计，TI ADC内的跟踪保持（T / H）电路的滤波特性的调整也是困难的。这里，提供了使用采样开关的栅极电压的变化（其改变采样开关的“开”电阻）的T / H电路架构，以改变T / H电路的带宽，以便精确匹配带宽。

42. 发明申请

US20130265732A1 INTERCHIP COMMUNICATION USING A DIELECTRIC WAVEGUIDE 有权
标题翻译：使用介质波导的交互通信
公开(公告)号：US20130265732A1
公开(公告)日：2013-10-10
申请号：US13439557
申请日：2012-04-04
申请人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
发明人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
IPC分类号： H05K1/11 , H05K1/18
CPC分类号： H05K1/0239 , G02B6/12004 , G02B6/1228 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/121 , H01P3/16 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K1/115 , H05K1/18 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装基板和集成电路（IC）的电路组件。封装衬底具有微带线，并且IC被固定到封装衬底并且电耦合到微带线。电路板也固定到封装衬底。介质波导固定在电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域的介质芯，并且微带线被配置为与介质波导形成通信链路。

43. 发明授权

US08513980B2 Reduced offset comparator 有权
标题翻译：减少偏移比较器
公开(公告)号：US08513980B2
公开(公告)日：2013-08-20
申请号：US13281227
申请日：2011-10-25
申请人： Robert F. Payne , Baher S. Haroun
发明人： Robert F. Payne , Baher S. Haroun
IPC分类号： H03K5/22
CPC分类号： H03K5/2481
摘要： An apparatus is provided. The apparatus comprises backend circuitry and pairs of redundant input circuits. Each pair of redundant input circuits is configured to form a differential pair of transistors, and each redundant input circuit includes a multiplexer and a set of transistors. The multiplexer is coupled to the backend circuitry, and each transistor from the set of transistors has a first passive electrode, a second passive electrode, and a control electrode. The first passive electrode of each transistor from the set of transistors is coupled to the multiplexer, and the control electrodes from the set of transistors are coupled together.
摘要翻译：提供了一种装置。该装置包括后端电路和冗余输入电路对。每对冗余输入电路被配置为形成差分对晶体管，并且每个冗余输入电路包括多路复用器和一组晶体管。多路复用器耦合到后端电路，并且来自该组晶体管的每个晶体管具有第一无源电极，第二无源电极和控制电极。来自晶体管组的每个晶体管的第一无源电极耦合到多路复用器，并且来自该组晶体管的控制电极耦合在一起。

44. 发明授权

US08248290B2 Multiplexed amplifier with reduced glitching 有权
标题翻译：复用放大器减少了毛刺
公开(公告)号：US08248290B2
公开(公告)日：2012-08-21
申请号：US12880311
申请日：2010-09-13
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03M1/34
CPC分类号： H03M1/0872 , H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.
摘要翻译：在使用以小于50％工作周期工作的放大器的许多应用中，减少数量放大器以降低功耗将是有利的。这里，提供了一种放大器，其被时分复用以容纳多个数据路径。此外，在该放大器的输出端子处提供复位电路或复位机构，以短暂地输出端子短路，以防止可能由数据路径之间切换引起的毛刺。

45. 发明授权

US08248282B2 Track and hold architecture with tunable bandwidth 有权
标题翻译：跟踪和保持具有可调带宽的架构
公开(公告)号：US08248282B2
公开(公告)日：2012-08-21
申请号：US12857674
申请日：2010-08-17
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03M1/00
CPC分类号： H03M1/08 , H03M1/1215
摘要： To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.
摘要翻译：到目前为止，时间交织（TI）模数转换器（ADC）中的带宽不匹配已被大大忽略，因为通过数字后处理（即有限脉冲响应滤波器）执行带宽不匹配的补偿。然而，数字后处理的滞后在高速系统中是禁止的，表明需要盲目错配补偿。即使使用盲带宽失配估计，TI ADC内的跟踪保持（T / H）电路的滤波特性的调整也是困难的。这里，提供了使用采样开关的栅极电压的变化（其改变采样开关的“开”电阻）的T / H电路架构，以改变T / H电路的带宽，以便精确匹配带宽。

46. 发明授权

US07990188B2 Clock buffer 有权
标题翻译：时钟缓冲
公开(公告)号：US07990188B2
公开(公告)日：2011-08-02
申请号：US13017436
申请日：2011-01-31
申请人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
发明人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
IPC分类号： H03B1/00
CPC分类号： H03M1/002 , H03M1/1245
摘要： An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs.
摘要翻译：提供了一种装置。该装置包括具有第一BJT和第二BJT的第一双极结型晶体管（BJT）差分对，具有第三BJT和第四BJT的第二BJT差分对，具有第五BJT和第六BJT的第一钳位，以及第二夹具具有第七BJT和第八BJT。第三BJT的集电极和基极分别耦合到第一BJT的集电极和基极，并且第四BJT的集电极和基极分别耦合到第二BJT的集电极和基极。第一，第二，第三和第四BJT的基极接收输入时钟信号。第五和第六BJT的发射器耦合到第一和第三BJT的集电极，而第七和第八BJT的发射极耦合到第二和第四BJT的集电极。第五和第七BJT的基极适于接收低钳位电压，并且第六和第八BJT的基极适于接收高钳位电压。另外，第一和第二夹具耦合到第一，第二，第三和第四BJT的收集器。

47. 发明授权

US07906995B2 Clock buffer 有权
公开(公告)号：US07906995B2
公开(公告)日：2011-03-15
申请号：US12393188
申请日：2009-02-26
申请人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
发明人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
IPC分类号： H03B1/00
CPC分类号： H03M1/002 , H03M1/1245
摘要： An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs.

48. 发明授权

US07825846B2 Error correction method and apparatus 有权
标题翻译：纠错方法及装置
公开(公告)号：US07825846B2
公开(公告)日：2010-11-02
申请号：US12393207
申请日：2009-02-26
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03M1/38
CPC分类号： G05F3/265
摘要： A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor.
摘要翻译：提供开关电流源。开关电流源通常由晶体管和电阻组成，源极具有高输出阻抗。与切换的电流源一起包括纠错晶体管和电阻器，其协作以通过偏置晶体管馈送电流以校正通常由开关电流源内的晶体管的电流增益或电流导致的误差。然而，为了实现这一点，电阻器被选择为具有足够大的值，使得来自误差校正晶体管的电流流过偏置晶体管。

49. 发明授权

US07688125B2 Latched comparator and methods for using such 有权
标题翻译：锁存比较器和使用方法
公开(公告)号：US07688125B2
公开(公告)日：2010-03-30
申请号：US11626860
申请日：2007-01-25
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/2885
摘要： Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a preamplifier circuit, a latch circuit and a current re-use circuit. The current re-use circuit applies a current to the preamplifier circuit during a transparent phase, and applies a similar current to the latch circuit during a latch phase.
摘要翻译：本文公开了用于比较信号的各种系统和方法。例如，本发明的一些实施例为比较器电路提供前置放大器电路，锁存电路和电流重用电路。当前的再利用电路在透明相位期间向前置放大器电路施加电流，并且在锁存阶段期间向闩锁电路施加类似的电流。

50. 发明申请

US20090219060A1 METHOD AND APPARATUS OF SFDR ENHANCEMENT 有权
标题翻译： SFDR增强的方法和装置
公开(公告)号：US20090219060A1
公开(公告)日：2009-09-03
申请号：US12393182
申请日：2009-02-26
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： G11C27/02 , H03K3/00
CPC分类号： H03M1/0836 , G11C27/026 , H03M1/0682 , H03M1/069 , H03M1/1245 , H03M1/164
摘要： A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and conventional S/H circuits is the use of a peaking circuit. This peaking circuit generally provides increased current to switching transistor when transitioning between track and hold which can increase the Spurious-Free Dynamic Range (SFDR) as low frequencies, by as much as 15 dB.
摘要翻译：提供了用于模数转换器（ADC）的跟踪保持或采样保持（S / H）电路。所公开的S / H电路和常规S / H电路之间的区别在于使用峰值电路。该峰值电路通常在轨道和保持之间转换时向开关晶体管提供增加的电流，这可以将无杂散动态范围（SFDR）降低多达15 dB。

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