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41. 发明授权

US08043913B2 Method of forming trench-gate field effect transistors 有权
标题翻译：形成沟槽栅场效应晶体管的方法
公开(公告)号：US08043913B2
公开(公告)日：2011-10-25
申请号：US13075091
申请日：2011-03-29
申请人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
发明人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
摘要翻译：形成场效应晶体管的方法包括：在半导体区域中形成沟槽; 在沟槽中形成屏蔽电极; 执行第一导电类型的杂质的成角度的侧壁注入，以形成与沟槽相邻的沟道增强区域; 在半导体区域中形成第二导电类型的体区; 并且在所述体区域中形成所述第一导电类型的源极区域，所述源极区域和所述体区域与所述半导体区域之间的界面在所述体区域中形成沟道区域，所述沟道区域沿着所述沟槽侧壁延伸。沟道增强区域部分地延伸到沟道区的下部，从而减小沟道区的电阻。

42. 发明申请

US20100315159A1 HIGH VOLTAGE POWER INTEGRATED CIRCUIT 有权
标题翻译：高压电力综合电路
公开(公告)号：US20100315159A1
公开(公告)日：2010-12-16
申请号：US12815766
申请日：2010-06-15
申请人： Christopher Boguslaw Kocon , John Manning Savidge Neilson , Simon John Molloy , Haian Lin , Charles Walter Pearce
发明人： Christopher Boguslaw Kocon , John Manning Savidge Neilson , Simon John Molloy , Haian Lin , Charles Walter Pearce
IPC分类号： H01L25/00 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L27/088 , H01L29/0847 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/66659 , H01L29/66681 , H01L29/7816
摘要： A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.
摘要翻译：由n型衬底上形成的两个电荷平衡，扩展漏极NMOS晶体管（CBDEMOS）组成的高性能功率集成电路。具有n型衬底源的CBDENMOS晶体管。具有n型衬底的电荷平衡沟道二极管（CBCD）。一种用于形成由在n衬底上形成的两个CBDENMOS晶体管组成的高性能功率集成电路的工艺。一种在n型衬底上形成由一个CBDENMOS晶体管和一个CBCD组成的功率集成电路的工艺。

43. 发明申请

US20100006927A1 Charge Balance Techniques for Power Devices 有权
标题翻译：电力设备的充电平衡技术
公开(公告)号：US20100006927A1
公开(公告)日：2010-01-14
申请号：US12562025
申请日：2009-09-17
申请人： Christopher Boguslaw Kocon
发明人： Christopher Boguslaw Kocon
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/402 , H01L29/41741
摘要： A vertically-conducting charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current along a vertical dimension when biased in a conducting state, and a non-active perimeter region surrounding the active area. No current flows along the vertical dimension through the non-active perimeter region when the plurality of cells is biased in the conducting state. Strips of p pillars and strips of n pillars are arranged in an alternating manner. The strips of p pillars have a depth extending along the vertical dimension, a width, and a length. The strips of p and n pillars extend through both the active area and the non-active perimeter region along a length of a die that contains the semiconductor power device. The length of the die extends parallel to the length of the strips of p pillars. Each of the strips of p pillars includes a plurality of discontinuities forming portions of a plurality of strips of n regions. The plurality of strips of n regions extends in the non-active perimeter region perpendicular to the length of the die.
摘要翻译：垂直导电的电荷平衡半导体功率器件包括有源区域，该有源区域包括多个能够沿导电状态偏置时沿垂直尺寸传导电流的单元，以及围绕有源区域的非有效周边区域。当多个单元被偏置在导通状态时，没有电流沿着垂直尺寸流过非活动周边区域。 p柱和n柱的条带以交替的方式排列。 p柱的条具有沿垂直尺寸，宽度和长度延伸的深度。 p和n柱的条沿着包含半导体功率器件的管芯的长度延伸穿过有效区域和非有效周边区域。模具的长度平行于p柱的条带的长度延伸。 p柱的每个条带包括形成n个区域的多个条带的部分的多个不连续部。 n个区域的多个条带在垂直于管芯长度的非活动周边区域中延伸。

44. 发明申请

US20090230465A1 Trench-Gate Field Effect Transistors and Methods of Forming the Same 审中-公开
标题翻译：沟槽栅场效应晶体管及其形成方法
公开(公告)号：US20090230465A1
公开(公告)日：2009-09-17
申请号：US12404909
申请日：2009-03-16
申请人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
发明人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
IPC分类号： H01L29/772
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.
摘要翻译：场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的体区。栅极沟槽延伸穿过身体区域并终止在半导体区域内。至少一个导电屏蔽电极设置在栅极沟槽中。栅极电极设置在栅极沟槽中，但与至少一个导电屏蔽电极绝缘。屏蔽介电层绝缘至少一个导电屏蔽电极与半导体区域。栅极电介质层使栅电极与体区绝缘。屏蔽电介质层形成为使其伸出并直接延伸到身体区域下方。

45. 发明申请

US20090179264A1 LDMOS INTEGRATED SCHOTTKY DIODE 有权
标题翻译： LDMOS集成肖特基二极管
公开(公告)号：US20090179264A1
公开(公告)日：2009-07-16
申请号：US12014581
申请日：2008-01-15
申请人： Jacek Korec , Shuming Xu , Christopher Boguslaw Kocon
发明人： Jacek Korec , Shuming Xu , Christopher Boguslaw Kocon
IPC分类号： H01L27/06 , H01L29/872
CPC分类号： H01L27/0727 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/40 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7806 , H01L29/782 , H01L29/872
摘要： A semiconductor device includes a substrate having a first conductivity type and a semiconductor layer formed over the substrate and having lower and upper surfaces. A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device is formed over the substrate and includes a source region of the first conductivity type and a drain extension region of the first conductivity type formed in the semiconductor layer proximate the upper surface of the semiconductor layer, and a drain contact electrically connecting the drain extension region to the substrate. A Schottky diode is formed over the substrate and includes at least one doped region of the first conductivity type formed in the semiconductor layer proximate to the upper surface, an anode contact forming a Schottky barrier with the at least one doped region, and a cathode contact laterally spaced from the anode contact and electrically connecting at least one doped region to the substrate.
摘要翻译：半导体器件包括具有第一导电类型的衬底和形成在衬底上并具有下表面和上表面的半导体层。横向扩散的金属氧化物半导体（LDMOS）晶体管器件形成在衬底上，并且包括第一导电类型的源极区域和形成在靠近半导体的上表面的半导体层中的第一导电类型的漏极延伸区域以及将漏极延伸区域与衬底电连接的漏极接触。肖特基二极管形成在衬底之上，并且包括形成在靠近上表面的半导体层中的至少一个第一导电类型的掺杂区域，形成具有至少一个掺杂区域的肖特基势垒的阳极接触器和阴极接触器与阳极接触件横向间隔开并将至少一个掺杂区域电连接到衬底。

46. 发明授权

US06991977B2 Method for forming a semiconductor structure with improved smaller forward voltage loss and higher blocking capability 失效
标题翻译：用于形成具有改善的较小的正向电压损耗和更高的阻断能力的半导体结构的方法
公开(公告)号：US06991977B2
公开(公告)日：2006-01-31
申请号：US10666034
申请日：2003-09-18
申请人： Christopher Boguslaw Kocon
发明人： Christopher Boguslaw Kocon
IPC分类号： H01L21/8238
CPC分类号： H01L29/407 , H01L29/404 , H01L29/41766 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is formed as follows. A semiconductor substrate having a first region of a first conductivity type is provided. A region of a second conductivity type is formed in the semiconductor substrate such that the first and second regions form a p-n junction. First and second charge control electrodes are formed adjacent to but insulated from one of the first and second regions, along a dimension parallel to flow of current through the semiconductor device, wherein the first charge control electrode is adapted to be biased differently than the second charge control electrode.
摘要翻译：如下形成半导体器件。提供具有第一导电类型的第一区域的半导体衬底。在半导体衬底中形成第二导电类型的区域，使得第一和第二区域形成p-n结。第一和第二电荷控制电极沿着平行于通过半导体器件的电流流动的尺寸形成为邻近于第一和第二区域之一但与其中之一绝缘，其中第一电荷控制电极适于与第二电荷不同地偏置控制电极。

47. 发明授权

US06285056B1 Conductivity enhanced MOS-gated semiconductor devices 失效
标题翻译：电导率增强MOS门控半导体器件
公开(公告)号：US06285056B1
公开(公告)日：2001-09-04
申请号：US09114769
申请日：1998-07-14
申请人： Christopher Boguslaw Kocon
发明人： Christopher Boguslaw Kocon
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/1095 , H01L29/36 , H01L29/66712 , H01L29/7395
摘要： The resistance to current flow through an MOS-gated semiconductor device is reduced by providing a high conductivity region in the path of current through the drain region, but so positioned relative to the p-n voltage blocking junction of the device so as not to adversely affect the voltage blocking capability of the p-n junction. In one embodiment, the drain region is made of higher than normal electrical conductivity, but a diffused, graded p-n junction is provided for extending the low conductivity portion of the drain region bordering the p-n junction further than usual into the drain region.
摘要翻译：通过在通过漏极区域的电流的路径中提供高导电性区域，而相对于器件的pn电压阻挡接合点定位，从而降低了通过MOS栅控半导体器件的电流流动阻力，从而不会不利地影响 pn结的电压阻断能力。在一个实施例中，漏区由高于正常导电率制成，但是扩散的渐变p-n结被提供用于将p-n结邻接的漏极区的低导电部分比通常延伸到漏极区。

48. 发明授权

US08928075B2 Power integrated circuit including series-connected source substrate and drain substrate power MOSFETs 有权
标题翻译：功率集成电路包括串联源极衬底和漏极衬底功率MOSFET
公开(公告)号：US08928075B2
公开(公告)日：2015-01-06
申请号：US13563923
申请日：2012-08-01
申请人： Christopher Boguslaw Kocon , Marie Denison , Taylor Efland
发明人： Christopher Boguslaw Kocon , Marie Denison , Taylor Efland
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L27/0922 , H01L29/0634 , H01L29/0649 , H01L29/0696 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4933 , H01L29/7802 , H01L29/7803 , H01L29/7809 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.
摘要翻译：一种半导体器件，其包含在下漏极层上方具有漏极漂移区域的高电压MOS晶体管和横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过漏极漂移区域和与通道电流流动平行的体区域。 RESURF沟槽在衬垫上具有电介质衬垫和导电RESURF元件。源接触金属设置在身体区域和源区域上。一种半导体器件，其包含在下漏极层上具有漏极漂移区域的高电压MOS晶体管，以及横向设置在衬底顶表面处的沟道区域。 RESURF沟槽穿过垂直于沟道电流的漏极漂移区域和体区。源极接触金属设置在源极接触沟槽中并在漏极漂移区域上延伸以提供场板。

49. 发明授权

US08803207B2 Shielded gate field effect transistors 有权
标题翻译：屏蔽栅场效应晶体管
公开(公告)号：US08803207B2
公开(公告)日：2014-08-12
申请号：US13081400
申请日：2011-04-06
申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa
发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa
IPC分类号： H01L29/76 , H01L29/66
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.
摘要翻译：在一个一般方面，一种装置可以包括设置在半导体区域中的沟槽，衬在沟槽的侧壁的下部的屏蔽电介质层和沟槽的底表面，以及衬在该侧壁的上部的栅极电介质的沟槽。该设备还可以包括设置在沟槽的下部并由屏蔽电介质层与半导体区域绝缘的屏蔽电极，以及设置在屏蔽电极上的沟槽中的电极间电介质（IED），其中屏蔽电极具有一个弯曲的顶面。

50. 发明授权

US08796745B2 Monolithically integrated active snubber 有权
标题翻译：单片整合主动缓冲器
公开(公告)号：US08796745B2
公开(公告)日：2014-08-05
申请号：US13540813
申请日：2012-07-03
申请人： Christopher Boguslaw Kocon
发明人： Christopher Boguslaw Kocon
IPC分类号： H01L27/14
CPC分类号： H01L29/66681 , H01L27/0629 , H01L27/0733 , H01L28/24 , H01L29/41741 , H01L29/41758 , H01L29/41766 , H01L29/66659 , H01L29/66727 , H01L29/7803 , H01L29/7835 , H01L29/94
摘要： A semiconductor device containing an extended drain MOS transistor with an integrated snubber formed by forming a drain drift region of the MOS transistor, forming a snubber capacitor including a capacitor dielectric layer and capacitor plate over the extended drain, and forming a snubber resistor over a gate of the MOS transistor so that the resistor is connected in series between the capacitor plate and a source of the MOS transistor.
摘要翻译：一种半导体器件，其包含具有集成缓冲器的扩展漏极MOS晶体管，该集成缓冲器通过形成MOS晶体管的漏极漂移区域，在扩展漏极上形成包括电容器介电层和电容器板的缓冲电容器，并在栅极上形成缓冲电阻器使得电阻器串联连接在电容器板和MOS晶体管的源极之间。

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