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41. 发明申请

US20100200977A1 Layered chip package and method of manufacturing same 有权
标题翻译：分层芯片封装及其制造方法
公开(公告)号：US20100200977A1
公开(公告)日：2010-08-12
申请号：US12320884
申请日：2009-02-06
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
IPC分类号： H01L23/48 , H01L21/98
CPC分类号： H01L25/0657 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/49 , H01L24/82 , H01L24/94 , H01L24/96 , H01L25/50 , H01L2221/68359 , H01L2223/54426 , H01L2224/05554 , H01L2224/18 , H01L2224/32145 , H01L2224/48 , H01L2224/48463 , H01L2224/49175 , H01L2224/4943 , H01L2224/73267 , H01L2224/94 , H01L2225/06551 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10161 , H01L2924/10253 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/03
摘要： A layered chip package has a main body including a plurality of pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The plurality of pairs of layer portions include at least one specific pair of layer portions consisting of a first-type layer portion and a second-type layer portion. The first-type layer portion includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. A layered substructure formed of a stack of two substructures each of which includes a plurality of preliminary layer portions aligned is used to fabricate a stack of a predetermined two or greater number of pairs of layer portions, and the main body is fabricated by stacking an additional first-type layer portion together with the stack, the number of the additional first-type layer portion being equal to the number of the specific pair(s) of layer portions included in the stack.
摘要翻译：分层芯片封装具有主体，该主体包括多对层部分，布线设置在主体的侧表面上。每个层部分包括半导体芯片。多个层部分包括由第一类型层部分和第二类型的部分组成的至少一个特定的一对层部分。第一型层部分包括多个电极，每个电极各自连接到半导体芯片，并且每个电极具有位于布置在其上的主体的侧表面的端面，而第二类型层部分不包括电极。由堆叠的两个子结构形成的分层子结构，每个子结构包括多个对齐的预备层部分，用于制造预定的两个或更多数量的层部分的堆叠，并且主体通过堆叠附加的第一型层部分与堆叠一起，附加的第一类型层部分的数量等于堆叠中包括的层部分的特定对的数量。

42. 发明申请

US20090315189A1 Layered chip package and method of manufacturing same 有权
标题翻译：分层芯片封装及其制造方法
公开(公告)号：US20090315189A1
公开(公告)日：2009-12-24
申请号：US12213645
申请日：2008-06-23
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki
IPC分类号： H01L23/48 , H01L21/58
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/544 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/82 , H01L24/95 , H01L25/0657 , H01L2221/68359 , H01L2223/5442 , H01L2223/54426 , H01L2224/24145 , H01L2224/48463 , H01L2224/4943 , H01L2225/06551 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/181 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.
摘要翻译：层状芯片封装包括具有多个层部分的主体和布置在主体的侧表面上的布线。每层部分包括半导体芯片，覆盖半导体芯片的至少一个侧表面的绝缘部分和连接到半导体芯片的多个电极。该绝缘部具有位于配置有布线的主体的侧面的端面。每个电极具有由绝缘部分包围并位于布置有布线的主体的侧表面处的端面。为了制造分层芯片封装，通过以下步骤制造分层芯片封装子结构：处理半导体晶片以形成对准的多个预半导体芯片部分; 形成至少一个延伸到与所述预半导体芯片部分中的至少一个相邻的凹槽; 形成绝缘层以填充凹槽; 并形成电极。

43. 发明授权

US08513034B2 Method of manufacturing layered chip package 有权
标题翻译：分层芯片封装的制造方法
公开(公告)号：US08513034B2
公开(公告)日：2013-08-20
申请号：US13064880
申请日：2011-04-22
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , G11C16/102 , H01L24/01 , H01L25/50 , H01L2224/48091 , H01L2225/06527 , H01L2225/06551 , H01L2225/06596 , H01L2924/07802 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body. Each substructure is fabricated through the steps of: fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions aligned; distinguishing between a normally functioning pre-semiconductor-chip portion and a malfunctioning pre-semiconductor-chip portion among the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer; and forming electrodes connected to the normally functioning pre-semiconductor-chip portion and having respective end faces located in the side surface of the main body on which the wiring is disposed, without forming any electrode connected to the malfunctioning pre-semiconductor-chip portion.
摘要翻译：一种制造包括主体和布置在主体的侧表面上的布线的分层芯片封装的方法。主体包括多个层部分。该方法包括制造多个子结构，并且通过使用多个子结构制造主体并且通过在主体上形成布线来完成分层芯片封装。每个子结构通过以下步骤制造：制造包括对准的多个预半导体芯片部分的预底晶片; 区分预结晶晶片中包含的多个预半导体芯片部分中的正常工作的预半导体芯片部分和故障的预半导体芯片部分; 以及形成连接到正常工作的预半导体芯片部分并且具有位于布置有布线的主体的侧表面中的各个端面的电极，而不形成连接到故障的预半导体芯片部分的任何电极。

44. 发明授权

US08455349B2 Layered chip package and method of manufacturing same 有权
标题翻译：分层芯片封装及其制造方法
公开(公告)号：US08455349B2
公开(公告)日：2013-06-04
申请号：US12769361
申请日：2010-04-28
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima , Tatsuya Harada
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima , Tatsuya Harada
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L21/6835 , H01L22/22 , H01L23/3121 , H01L23/481 , H01L24/05 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/04105 , H01L2224/05551 , H01L2224/05554 , H01L2224/24146 , H01L2224/32145 , H01L2224/73267 , H01L2224/82005 , H01L2224/82101 , H01L2224/83005 , H01L2224/8385 , H01L2224/9202 , H01L2224/96 , H01L2225/06541 , H01L2225/06565 , H01L2924/01029 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1441 , H01L2924/1453 , H01L2924/181 , H01L2224/03 , H01L2924/00
摘要： A layered chip package includes a main body and a plurality of through electrodes. The main body includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions. The plurality of through electrodes are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions. Each of the plurality of layer portions includes a semiconductor chip. At least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes. The wiring includes a plurality of conductors that make contact with a through electrode that is exposed in the wall faces of any one of the plurality of through holes and passes through the through hole.
摘要翻译：分层芯片封装包括主体和多个贯通电极。主体包括层叠的多个层部分和穿透所有多个层部分的多个通孔。多个贯通电极设置在主体的多个通孔中，并穿透所有多个层部分。多个层部分中的每一个包括半导体芯片。多个层部分中的至少一个包括将半导体芯片电连接到多个贯通电极的布线。布线包括多个导体，其与暴露在多个通孔中的任一个的壁面中的穿通电极接触并穿过通孔。

45. 发明申请

US20110266692A1 LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：层状芯片包装及其制造方法
公开(公告)号：US20110266692A1
公开(公告)日：2011-11-03
申请号：US12769361
申请日：2010-04-28
申请人： Yoshitaka SASAKI , Hiroyuki Ito , Atsushi Iijima , Tatsuya Harada
发明人： Yoshitaka SASAKI , Hiroyuki Ito , Atsushi Iijima , Tatsuya Harada
IPC分类号： H01L23/48 , H01L21/50 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/6835 , H01L22/22 , H01L23/3121 , H01L23/481 , H01L24/05 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/04105 , H01L2224/05551 , H01L2224/05554 , H01L2224/24146 , H01L2224/32145 , H01L2224/73267 , H01L2224/82005 , H01L2224/82101 , H01L2224/83005 , H01L2224/8385 , H01L2224/9202 , H01L2224/96 , H01L2225/06541 , H01L2225/06565 , H01L2924/01029 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1441 , H01L2924/1453 , H01L2924/181 , H01L2224/03 , H01L2924/00
摘要： A layered chip package includes a main body and a plurality of through electrodes. The main body includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions. The plurality of through electrodes are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions. Each of the plurality of layer portions includes a semiconductor chip. At least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes. The wiring includes a plurality of conductors that make contact with a through electrode that is exposed in the wall faces of any one of the plurality of through holes and passes through the through hole.
摘要翻译：分层芯片封装包括主体和多个贯通电极。主体包括层叠的多个层部分和穿透所有多个层部分的多个通孔。多个贯通电极设置在主体的多个通孔中，并穿透所有多个层部分。多个层部分中的每一个包括半导体芯片。多个层部分中的至少一个包括将半导体芯片电连接到多个贯通电极的布线。布线包括多个导体，其与暴露在多个通孔中的任一个的壁面中的穿通电极接触并穿过通孔。

46. 发明授权

US07964976B2 Layered chip package and method of manufacturing same 有权
标题翻译：分层芯片封装及其制造方法
公开(公告)号：US07964976B2
公开(公告)日：2011-06-21
申请号：US12222955
申请日：2008-08-20
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , G11C16/102 , H01L24/01 , H01L25/50 , H01L2224/48091 , H01L2225/06527 , H01L2225/06551 , H01L2225/06596 , H01L2924/07802 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.
摘要翻译：层状芯片封装包括具有多个层部分的主体和布置在主体的侧表面上的布线。多个层部分包括第一类型的至少一个层部分和第二类型的至少一个层部分。第一和第二类型的层部分都包括半导体芯片。第一类型的层部分还包括多个电极，每个电极连接到半导体芯片，并且每个电极具有位于布置有布线的主体的侧表面的端面，而第二类型的层部分不包括连接到半导体芯片并且具有位于布置有布线的主体的侧表面的端面的任何电极。布线连接到多个电极中的每一个的端面。

47. 发明授权

US07846772B2 Layered chip package and method of manufacturing same 有权
标题翻译：分层芯片封装及其制造方法
公开(公告)号：US07846772B2
公开(公告)日：2010-12-07
申请号：US12213645
申请日：2008-06-23
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki
IPC分类号： H01L21/00
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/544 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/82 , H01L24/95 , H01L25/0657 , H01L2221/68359 , H01L2223/5442 , H01L2223/54426 , H01L2224/24145 , H01L2224/48463 , H01L2224/4943 , H01L2225/06551 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/181 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.
摘要翻译：层状芯片封装包括具有多个层部分的主体和布置在主体的侧表面上的布线。每层部分包括半导体芯片，覆盖半导体芯片的至少一个侧表面的绝缘部分和连接到半导体芯片的多个电极。该绝缘部具有位于配置有布线的主体的侧面的端面。每个电极具有由绝缘部分包围并位于布置有布线的主体的侧表面处的端面。为了制造分层芯片封装，通过以下步骤制造分层芯片封装子结构：处理半导体晶片以形成对准的多个预半导体芯片部分; 形成至少一个延伸到与所述预半导体芯片部分中的至少一个相邻的凹槽; 形成绝缘层以填充凹槽; 并形成电极。

48. 发明申请

US20100270414A1 SEAT BELT RETRACTOR 有权
标题翻译：座椅皮带扣
公开(公告)号：US20100270414A1
公开(公告)日：2010-10-28
申请号：US12756420
申请日：2010-04-08
申请人： Tatsuya Harada , Hiroko Yoshikawa
发明人： Tatsuya Harada , Hiroko Yoshikawa
IPC分类号： B60R22/34
CPC分类号： B60R22/46 , B60R22/1952 , B60R2021/01006 , B60R2022/4666
摘要： A seat belt retractor may include: a motor that generates a driving force for retracting and unreeling a seat belt by rotating a shaft, a gear case has an interior portion that houses a gear that converts a rotary force of the shaft into a driving force, a harness connected to a side of the motor including the shaft that is disposed opposite the gear case, a motor case having an opening disposed in only one end thereof, and a motor cap disposed on a side of the motor including the shaft opposing the gear case. The motor cap may include a passage portion through which the harness passes to an exterior thereof. The opening in the motor case may be sealed by attaching the motor case to the motor cap and the gear case in a sandwiched manner.
摘要翻译：安全带卷收器可以包括：马达，其产生用于通过旋转轴来缩回和释放座椅安全带的驱动力;齿轮箱具有容纳将轴的旋转力转换为驱动力的齿轮的内部，连接到电动机侧的线束，其包括与齿轮箱相对设置的轴，马达壳体，其具有仅在其一端设置的开口;以及马达盖，其设置在马达的侧面，该马达包括与齿轮相对的轴案件。马达盖可以包括通道部分，线束穿过该通道部分到达其外部。电动机壳体中的开口可以通过将电动机壳体以夹持方式附接到电动机盖和齿轮箱来进行密封。

49. 发明授权

US07767494B2 Method of manufacturing layered chip package 有权
标题翻译：分层芯片封装的制造方法
公开(公告)号：US07767494B2
公开(公告)日：2010-08-03
申请号：US12216144
申请日：2008-06-30
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L23/544 , H01L21/67005 , H01L23/49805 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/82 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2223/5442 , H01L2223/54426 , H01L2223/54486 , H01L2224/24011 , H01L2224/24226 , H01L2224/274 , H01L2224/48091 , H01L2224/49 , H01L2225/06551 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/181 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure; bonding the first pre-polishing substructure to a jig such that a first surface of the first pre-polishing substructure faces the jig; forming a first substructure by polishing a second surface of the first pre-polishing substructure; bonding the second pre-polishing substructure to the first substructure such that a first surface of the second pre-polishing substructure faces the polished surface of the first substructure; and forming a second substructure by polishing a second surface of the second pre-polishing substructure.
摘要翻译：一种包括多个层部分的堆叠的层状芯片封装的制造方法，包括以下步骤：通过堆叠多个子结构来制造分层子结构，每个子结构包括对应于分层芯片的多个层部分的多个层部分包; 以及通过使用层状子结构制造多个分层芯片封装。制造层状子结构的步骤包括：制造第一和第二预抛光底层结构; 将第一预抛光次结构粘合到夹具，使得第一预抛光底座的第一表面面向夹具; 通过抛光所述第一预抛光子结构的第二表面来形成第一子结构; 将所述第二预抛光子结构粘合到所述第一子结构，使得所述第二预抛光下结构的第一表面面向所述第一子结构的抛光表面; 以及通过抛光所述第二预抛光次结构的第二表面来形成第二子结构。

50. 发明申请

US20090321957A1 Layered chip package and method of manufacturing same 有权
标题翻译：分层芯片封装及其制造方法
公开(公告)号：US20090321957A1
公开(公告)日：2009-12-31
申请号：US12216168
申请日：2008-06-30
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L25/0657 , H01L21/6835 , H01L23/544 , H01L24/24 , H01L24/82 , H01L24/92 , H01L24/95 , H01L25/0652 , H01L25/50 , H01L2221/68359 , H01L2223/5442 , H01L2223/54426 , H01L2224/24145 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/07802 , H01L2924/181 , H01L2924/30105 , H01L2924/00
摘要： A layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals.
摘要翻译：层状芯片封装包括：主体，其包括多个层部分; 布置在主体的侧表面上的布线; 设置在所述主体的上表面上的多个第一端子; 以及设置在主体的底面上的多个第二端子。每层部分包括半导体芯片，覆盖半导体芯片的至少一个侧表面的绝缘部分和连接到半导体芯片的多个电极。每个电极具有由绝缘部分包围并位于布置有布线的主体的侧表面处的端面。布线连接到多个层部分的多个电极的端面以及多个第一和第二端子。

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