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41. 发明授权

US08654291B2 Pixel circuit and display device 有权
标题翻译：像素电路和显示设备
公开(公告)号：US08654291B2
公开(公告)日：2014-02-18
申请号：US13504074
申请日：2010-10-21
申请人： Naoki Ueda , Yoshimitsu Yamauchi , Fumiki Nakano
发明人： Naoki Ueda , Yoshimitsu Yamauchi , Fumiki Nakano
IPC分类号： G02F1/1337
CPC分类号： G09G3/367 , G02F1/13624 , G09G3/3618 , G09G3/3655 , G09G3/3659 , G09G2300/0814 , G09G2300/0876
摘要： A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.
摘要翻译：提供了一种在不降低开口率的情况下实现低功耗的显示装置。液晶电容元件Clc被夹在像素电极20和相对电极80之间。像素电极20，第一开关电路22的一端，第二开关电路23的一端和第二晶体管T2的第一端形成内部节点N1。第一开关电路22和第二开关电路23的其他端子连接到源极线SL。第二开关电路23是由第一晶体管T1和二极管D1组成的串联电路。第一晶体管T1的控制端子，第二晶体管T2的第二端子和升压电容元件Cbst的一端形成输出节点N2。升压电容元件Cbst的另一端和第二晶体管T2的控制端分别连接到升压线BST和基准线REF。二极管D1具有从源极线SL到内部节点N1的整流功能。

42. 发明授权

US08576628B2 Nonvolatile random access memory 失效
标题翻译：非易失性随机存取存储器
公开(公告)号：US08576628B2
公开(公告)日：2013-11-05
申请号：US12863234
申请日：2009-01-06
申请人： Naoki Ueda
发明人： Naoki Ueda
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11521 , G11C16/0441
摘要： A nonvolatile random access memory that can be mounted on a substrate during a standard CMOS process. A memory cell comprises: a first MIS transistor including a first semiconductor layer of a first conductivity type in an electrically floating state, first drain and source regions of a second conductivity type formed on the first semiconductor layer, and a first gate electrode formed over the first semiconductor layer via a first gate insulating film; and a second MIS transistor including a second semiconductor layer of the first conductivity type isolated from the first semiconductor layer, second drain and source regions of the second conductivity type formed on the second semiconductor layer, a second gate electrode formed over the second semiconductor layer via a second gate insulating film. The first and second gate electrodes are electrically connected to each other so as to form a floating gate in an electrically floating state.
摘要翻译：一种非易失性随机存取存储器，可在标准CMOS工艺过程中安装在衬底上。存储单元包括：第一MIS晶体管，其包括处于浮置状态的第一导电类型的第一半导体层，形成在第一半导体层上的第二导电类型的第一漏极和源极区;以及第一栅电极，第一半导体层经由第一栅极绝缘膜; 以及第二MIS晶体管，包括从第一半导体层隔离的第一导电类型的第二半导体层，形成在第二半导体层上的第二导电类型的第二漏极和源极区，形成在第二半导体层上的第二栅电极第二栅极绝缘膜。第一和第二栅电极彼此电连接以形成处于浮动状态的浮动栅极。

43. 发明申请

US20130009163A1 SEMICONDUCTOR DEVICE, ACTIVE MATRIX SUBSTRATE, AND DISPLAY DEVICE 有权
标题翻译：半导体器件，有源矩阵衬底和显示器件
公开(公告)号：US20130009163A1
公开(公告)日：2013-01-10
申请号：US13636536
申请日：2010-11-04
申请人： Naoki Ueda
发明人： Naoki Ueda
IPC分类号： H01L29/788 , H01L27/15
CPC分类号： H01L27/11521 , G11C16/3418 , H01L27/11519 , H01L27/1156 , H01L27/1214 , H01L29/94
摘要： A semiconductor device that includes a substrate 37, a non-volatile memory (memory cell) 21 having a memory cell transistor (switching element) 33 and a floating gate electrode (memory storage part) 36, and a passivation insulating film (insulating layer) 40 and an organic polymer film (insulating layer) 41 both provided above the non-volatile memory 21, in which conductive wiring line layers (shielding part) 5a to 5c for shielding the floating gate electrode 36 are provided between the floating gate electrode 36 and both the passivation insulating film 40 and the organic polymer film 41 so that ions generated from the passivation insulating film 40 and the organic polymer film 41 can be prevented from reaching the floating gate electrode 36.
摘要翻译：一种半导体器件，包括衬底37，具有存储单元晶体管（开关元件）33和浮置栅电极（存储器存储部分）36的非易失性存储器（存储单元）21以及钝化绝缘膜（绝缘层） 40和在非易失性存储器21上方设置的有机聚合物膜（绝缘层）41，其中在浮动栅电极36和浮栅电极36之间设置有用于屏蔽浮栅电极36的导电布线层（屏蔽部）5a至5c 钝化绝缘膜40和有机聚合物膜41都可以防止从钝化绝缘膜40和有机聚合物膜41产生的离子到达浮栅电极36。

44. 发明授权

US08310638B2 Pixel circuit and display apparatus 有权
标题翻译：像素电路和显示设备
公开(公告)号：US08310638B2
公开(公告)日：2012-11-13
申请号：US13504609
申请日：2010-07-22
申请人： Yoshimitsu Yamauchi , Naoki Ueda , Fumiki Nakano
发明人： Yoshimitsu Yamauchi , Naoki Ueda , Fumiki Nakano
IPC分类号： G02F1/1337
CPC分类号： G09G3/3659 , G02F1/13624 , G09G2300/0465 , G09G2300/0876 , G09G2300/089 , G09G2310/08 , G09G2330/021
摘要： Disclosed is a display device that can achieve a reduction of power consumption without deteriorating the aperture ratio. A liquid crystal capacitance element (Clc) is formed by being sandwiched between a pixel electrode (20) and an opposite electrode (80). The pixel electrode (20), one end of a first switching circuit (22), one end of a second switching circuit (23), and the first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switching circuit (22) and the other end of the second switching circuit (23) are connected to a source line (SL). The second switching circuit (23) includes a series circuit of a transistor (T1) and a diode (D1), and an output node (N2) is formed of the control terminal of the transistor (T1), the second terminal of the transistor (T2), and one end of a boost capacitance element (Cbst). The other end of the boost capacitance element (Cbst) is connected to a boost line (BST), and the control terminal of the transistor (T2) is connected to a reference line (REF). The diode (D1) has a rectifying function in the direction to the internal node (N1) from the source line (SL).
摘要翻译：公开了一种能够在不损害开口率的情况下实现功耗的降低的显示装置。通过夹在像素电极（20）和相对电极（80）之间形成液晶电容元件（Clc）。像素电极（20），第一开关电路（22）的一端，第二开关电路（23）的一端和第二晶体管（T2）的第一端子形成内部节点（N1）。第一开关电路（22）的另一端和第二开关电路（23）的另一端连接到源极线（SL）。第二开关电路（23）包括晶体管（T1）和二极管（D1）的串联电路，输出节点（N2）由晶体管（T1）的控制端子形成，晶体管的第二端子（T2）和升压电容元件（Cbst）的一端。升压电容元件（Cbst）的另一端连接到升压线（BST），晶体管（T2）的控制端子连接到基准线（REF）。二极管（D1）在从源极线（SL）到内部节点（N1）的方向上具有整流功能。

45. 发明授权

US08028636B2 Stern shape of displacement-type marine vessel 有权
标题翻译：排水型船舶船尾形状
公开(公告)号：US08028636B2
公开(公告)日：2011-10-04
申请号：US12310232
申请日：2008-01-30
申请人： Reiko Takashima , Makoto Nishigaki , Toshinobu Sakamoto , Naoki Ueda , Kenichi Yamamoto
发明人： Reiko Takashima , Makoto Nishigaki , Toshinobu Sakamoto , Naoki Ueda , Kenichi Yamamoto
IPC分类号： B63B1/08
CPC分类号： B63H5/16 , B63B1/08 , B63B1/32 , B63B2001/325 , Y02T70/12 , Y02T70/127 , Y02T70/128
摘要： A stern shape of a displacement-type marine vessel enables reduction of the hull resistance and prevents propeller cavitation. The displacement-type marine vessel which travels in a velocity range in which the Froude number is smaller than the last hump and the stern includes knuckle lines connecting knuckle points provided on the surface of the hull, from a starting point in front of a propeller to an end point behind the propeller. A portion of the stern located inside the knuckle line in the direction of the width of the hull has a dome shape with upward curvature, and the length of the portion which has the dome shape is set to 10% or more of the entire hull length or at least the diameter of the propeller.
摘要翻译：位移式船舶的船尾形状能够降低船体阻力并防止螺旋桨气蚀。在弗劳德数小于最后一个驼峰的速度范围内行进的位移型海洋船只和船尾包括连接在船体表面上的转向节点的转向节，从螺旋桨前面的起点到螺旋桨后面的终点。位于转向节线内侧的船尾部分在船体宽度方向上具有向上弯曲的圆顶形状，并且具有圆顶形状的部分的长度设定为整个船体长度的10％以上或至少螺旋桨的直径。

46. 发明授权

US07903005B2 Method of transforming geographic coordinate 有权
标题翻译：变换地理坐标的方法
公开(公告)号：US07903005B2
公开(公告)日：2011-03-08
申请号：US12010924
申请日：2008-01-31
申请人： Naoki Ueda
发明人： Naoki Ueda
IPC分类号： H03M7/12
CPC分类号： G09B29/10 , G01C21/20 , G09B29/00
摘要： A method of transforming a geographic coordinate to a geographic location code includes the steps of: retrieving a latitude value and a longitude value of the geographic coordinate; quantizing the latitude value to a first integer value; quantizing the longitude value to a second integer value; converting the first integer value to a first code string, said first code string including a first digit representing a non-numeric character, a second digit representing a non-numeric character, and a third digit representing a numeric character; converting the second integer value to a second code string, said second code string including a fourth digit representing a non-numeric character, a fifth digit representing a non-numeric character, and a sixth digit representing a numeric character; and combining the first code string and the second code string to obtain the geographic location code having a fixed pattern of radix in a mixed radix notation system representation.
摘要翻译：将地理坐标变换为地理位置码的方法包括以下步骤：检索地理坐标的纬度值和经度值; 将纬度值量化为第一个整数值; 将经度值量化为第二整数值; 将所述第一整数值转换为第一代码串，所述第一代码串包括表示非数字字符的第一数字，表示非数字字符的第二数字和表示数字字符的第三数字; 将所述第二整数值转换为第二代码串，所述第二代码串包括表示非数字字符的第四数字，表示非数字字符的第五数字和表示数字字符的第六数字; 以及组合所述第一代码串和所述第二代码串，以获得具有固定模式的基数的地理位置代码。

47. 发明授权

US07728378B2 Nonvolatile semiconductor memory device, manufacturing method thereof and method of programming information into the memory device 失效
标题翻译：非易失性半导体存储器件及其制造方法以及将信息编程到存储器件中的方法
公开(公告)号：US07728378B2
公开(公告)日：2010-06-01
申请号：US11935945
申请日：2007-11-06
申请人： Naoki Ueda , Yoshimitsu Yamauchi
发明人： Naoki Ueda , Yoshimitsu Yamauchi
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/10 , H01L21/28282 , H01L27/105 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A nonvolatile semiconductor memory device capable of improving injection efficiency and simplifying manufacturing process is provided. The device comprises a memory cell having second conductive type of first impurity diffusion area and second impurity diffusion area on a first conductive type of semiconductor substrate, between the first and second impurity diffusion areas, a first laminate section formed by laminating a first insulating film, a charge storage layer, a second insulating film and a first gate electrode in this order from the bottom, and a second laminate section formed by laminating a third insulating film and a second gate electrode in this order from the bottom, wherein an area sandwiched between the first and second laminate sections is the second conductive type of a third impurity diffusion area having impurity density lower than that of the first and second impurity diffusion areas and not higher than 5×1012 ions/cm2.
摘要翻译：提供了一种能够提高注入效率并简化制造工艺的非易失性半导体存储器件。该装置包括在第一和第二杂质扩散区之间的第一导电类型的半导体衬底上具有第二导电类型的第一杂质扩散区和第二杂质扩散区的存储单元，通过层叠第一绝缘膜，电荷存储层，第二绝缘膜和第一栅极电极，以及从底部依次层叠第三绝缘膜和第二栅电极而形成的第二层叠部，其中夹在第一和第二层压体部分是具有比第一和第二杂质扩散区域低的杂质密度的第三杂质扩散区域的第二导电类型，并且不高于5×10 12离子/ cm 2。

48. 发明授权

US07236405B2 Method for setting erasing pulses and screening erasing defects of nonvolatile memory 有权
标题翻译：设置擦除脉冲和屏蔽非易失性存储器擦除缺陷的方法
公开(公告)号：US07236405B2
公开(公告)日：2007-06-26
申请号：US11251453
申请日：2005-10-14
申请人： Naoki Ueda
发明人： Naoki Ueda
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344 , G11C16/349
摘要： Method for determining the number of applications of erasing pulses, including extracting two pairs of the accumulated number of the erasing pulses Np and the ratio Re of the number of erased memory cells in the target block to be erased after the accumulated number of the erasing pulses Np has been applied, converting the two ratios Re into normalized variables S(Re) through normalizing the random variables of the normal distribution probability with standard deviations, converting the two accumulated numbers of the erasing pulses Np into common logarithms Log(Np), calculating a common logarithm Log(Nt) through extrapolating from two sets of coordinates [Log(Np), S(Re)], and determining the number of applications of the remaining erasing pulses so that the extrapolation erasing pulse number Nt is the target accumulated number of applications of erasing pulses.
摘要翻译：用于确定擦除脉冲的应用次数的方法，包括在累积的擦除脉冲数之后提取擦除脉冲Np的累积数目的两对和要擦除的目标块中的擦除存储器单元数量的比率Re 已经应用了Np，通过用标准偏差归一化正态分布概率的随机变量，将两个比率Re转换成归一化变量S（Re），将擦除脉冲Np的两个累加数转换成通用对数Log（Np），计算通过从两组坐标[Log（Np），S（Re）]进行外推的通常的对数Log（Nt），并且确定剩余擦除脉冲的应用次数，使得外推擦除脉冲数Nt是目标累加数的擦除脉冲的应用。

49. 发明授权

US07203095B2 Method for determining programming voltage of nonvolatile memory 失效
标题翻译：确定非易失性存储器编程电压的方法
公开(公告)号：US07203095B2
公开(公告)日：2007-04-10
申请号：US11251059
申请日：2005-10-14
申请人： Naoki Ueda
发明人： Naoki Ueda
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/04 , G11C16/12 , G11C16/3436 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50004
摘要： A method for determining programming voltage of a nonvolatile memory in which any variation in the threshold voltage at the memory cell after programming by hot carrier injection can be suppressed includes the steps of: setting the drain voltage to an initial setting level; applying the drain voltage and a gate voltage at a predetermined programming time; shifting the drain voltage to another setting level; reprogramming the memory cell with the another setting level of the drain voltage; measuring the threshold voltage of the memory cell; and determining a differential represented by a ratio of a change in the threshold voltage to a change in the drain voltage at the threshold voltage after the reprogramming, whereby when the determined differential and the measured threshold voltage remain within their respective permissible ranges, the setting determined by the shifting step is defined as an optimum level of the drain voltage.
摘要翻译：一种用于确定非易失性存储器的编程电压的方法，其中可以抑制通过热载流子注入编程之后的存储单元处的阈值电压的任何变化，包括以下步骤：将漏极电压设置为初始设置电平; 在预定的编程时间施加漏极电压和栅极电压; 将漏极电压移动到另一个设定电平; 以另一设定电平重新编程存储单元; 测量存储器单元的阈值电压; 并且确定由所述阈值电压的变化与所述重新编程之后的所述阈值电压下的所述漏极电压的变化的比率所表示的差值，由此当所确定的差值和所测量的阈值电压保持在其各自的允许范围内时，所述设定被确定通过移位步骤被定义为漏极电压的最佳电平。

50. 发明申请

US20050194119A1 Heat exchanger 失效
标题翻译：热交换器
公开(公告)号：US20050194119A1
公开(公告)日：2005-09-08
申请号：US11060603
申请日：2005-02-17
申请人： Yasutoshi Yamanaka , Haruhiko Watanabe , Naoki Ueda
发明人： Yasutoshi Yamanaka , Haruhiko Watanabe , Naoki Ueda
IPC分类号： F02B29/04 , F02M35/10 , F28F9/02
CPC分类号： F28F9/0224 , F28D2021/0082 , F28F9/02 , F28F9/0229 , F28F2009/029 , F28F2225/08
摘要： A heat exchanger according to the present invention has a plurality of tubes, header tanks and a support. Fluid flows through the plurality of tubes. The header tanks have a core plate and a tank body, and are disposed at longitudinal end portions of the plurality of tubes in such a manner to be communicated with internal spaces of the plurality of tubes. The core plate has approximately arc-shaped cross-section of which both side fringes are fixed onto the tank body and of which a middle portion fixes the longitudinal end portions of the plurality of tubes therein and bulges with respect to the both side fringes toward the plurality of tubes. The tank body and the core plate form an internal space of each of the header tanks. The support retains an interval between the both side fringes.
摘要翻译：根据本发明的热交换器具有多个管，集水箱和支撑件。流体流过多个管。集水箱具有芯板和罐体，并且以与多个管的内部空间连通的方式设置在多个管的纵向端部。芯板具有大致弧形的横截面，其两侧边缘固定在罐体上，其中间部分将多个管的纵向端部固定在其中，相对于两侧边缘朝向多个管。罐体和芯板形成每个集水箱的内部空间。支撑件保持两边条纹之间的间隔。

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