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41. 发明授权

US08437584B2 Optical I/O array module and its fabrication method 有权
标题翻译：光I / O阵列模块及其制作方法
公开(公告)号：US08437584B2
公开(公告)日：2013-05-07
申请号：US12844452
申请日：2010-07-27
申请人： Yasunobu Matsuoka , Toshiki Sugawara , Koichiro Adachi , Naoki Matsushima , Saori Hamamura , Madoka Minagawa , Norio Chujo
发明人： Yasunobu Matsuoka , Toshiki Sugawara , Koichiro Adachi , Naoki Matsushima , Saori Hamamura , Madoka Minagawa , Norio Chujo
IPC分类号： G02B6/26 , G02B6/42
CPC分类号： G02B6/43 , G02B6/4214 , G02B6/423 , H01S5/423 , Y10T29/49117
摘要： In fabricating an optical I/O array module, an optical waveguide provided with mirror parts, each having a tapered face, is formed on a substrate, a convex shaped member or a concave shaped member is placed at spots above the respective mirror parts of the optical waveguide, and laser diode arrays and photo diode arrays, provided with either a concave shape, or a convex shape, are mated with, or into the convex shaped member or the concave shaped member before being mounted. Further, there are formed multiple filmy layers, on which an LSI where a driver IC LSI of optical elements, and an amplifier LSI of the optical elements are integrated.
摘要翻译：在制造光学I / O阵列模块时，在衬底上形成具有锥面的镜部分的光波导，凸形或凹形的部件位于光波导，激光二极管阵列和具有凹形或凸形的光电二极管阵列在安装之前与凸形构件或凹形构件配合或配合。此外，形成有多个膜层，其上集成有光学元件的驱动器IC LSI和光学元件的放大器LSI的LSI。

42. 发明授权

US08358172B2 Peaking circuit, method for adjusting peaking circuit, differential amplifier installing peaking circuit, laser diode driving circuit installing peaking circuit, and data processing unit installing peaking circuit 有权
标题翻译：峰值电路，峰值电路调整方法，差分放大器安装峰值电路，激光二极管驱动电路安装峰值电路，数据处理单元安装峰值电路
公开(公告)号：US08358172B2
公开(公告)日：2013-01-22
申请号：US13023912
申请日：2011-02-09
申请人： Norio Chujo , Tsuneo Kawamata , Toshiaki Takai
发明人： Norio Chujo , Tsuneo Kawamata , Toshiaki Takai
IPC分类号： H03F3/45 , H03F3/191
CPC分类号： H03F3/45183 , H03F3/211 , H03F2203/45366 , H03F2203/45466 , H03F2203/45702 , H03F2203/45731
摘要： A peaking circuit for adjusting peaking of a high-frequency signal, comprises: a first inductor; a second inductor which is electromagnetically coupled with the first inductor; a signal input section which receives an input signal; a transistor which adjusts electric current passing through the second inductor according to the input signal inputted via the signal input section; and a signal output section which outputs a signal whose peaking has been adjusted by the first inductor. Mutual inductance of the electromagnetically coupled first and second inductors is changed by the adjustment of the electric current passing through the second inductor, according to the input signal inputted via the signal input section, with the use of the transistor, thereby adjusting the peaking of signal waveform of electric current passing through the first inductor, and the signal subjected to the peaking adjustment is outputted from the signal output section.
摘要翻译：一种用于调整高频信号峰值的峰值电路，包括：第一电感器; 与第一电感器电磁耦合的第二电感器; 信号输入部，其接收输入信号; 晶体管，其根据经由所述信号输入部输入的输入信号调整通过所述第二电感器的电流; 以及信号输出部，其输出由第一电感器调整了峰值的信号。根据通过信号输入部输入的输入信号，通过使用晶体管，通过调节通过第二电感器的电流来改变电磁耦合的第一和第二电感器的相互电感，由此调整信号的峰值从信号输出部输出通过第一电感器的电流波形和进行峰值调整的信号。

43. 发明授权

US08067984B2 Variable gain circuit 有权
标题翻译：可变增益电路
公开(公告)号：US08067984B2
公开(公告)日：2011-11-29
申请号：US12797121
申请日：2010-06-09
申请人： Takehito Kamimura , Norio Chujo
发明人： Takehito Kamimura , Norio Chujo
IPC分类号： H03G3/10
CPC分类号： H03G1/0088 , H03F3/72 , H03F2203/7206 , H03G1/0029 , H03G3/3084
摘要： There is provided a variable gain circuit system which is inductorless and capable of achieving a high gain and a wide band by elements for achieving variable gain to prevent decreasing a gain or deteriorating the band. The variable gain circuit includes: transistors; a resistor connected as a load of each transistor; a voltage source applying a bias voltage to each gate of the transistors; a switch selectively connecting the voltage source or a ground potential to each gate of the transistors in accordance with gain setting; and a current source connected to a common input. A drain of each transistor is connected to an input of a circuit in a subsequent stage.
摘要翻译：提供了一种可变增益电路系统，其是无电感的并且能够通过用于实现可变增益的元件实现高增益和宽带，以防止降低增益或使频带恶化。可变增益电路包括：晶体管; 作为每个晶体管的负载连接的电阻器; 对晶体管的每个栅极施加偏置电压的电压源; 开关根据增益设置选择性地将电压源或接地电位连接到晶体管的每个栅极; 以及连接到公共输入的电流源。每个晶体管的漏极在后续阶段连接到电路的输入端。

44. 发明授权

US08005130B2 Transmitter and receiver using forward clock overlaying link information 有权
标题翻译：发射机和接收机使用正向时钟叠加链路信息
公开(公告)号：US08005130B2
公开(公告)日：2011-08-23
申请号：US11826300
申请日：2007-07-13
申请人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
发明人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
IPC分类号： H04B1/38
CPC分类号： H04L7/0337
摘要： A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.
摘要翻译：一种在保持通信质量的同时减少数据信号线上的负载的发送和接收技术，从而可以提高数据信道的吞吐量。在收发机中，发射机侧具有将通过对链路信息进行编码而获得的比特序列发送到时钟信号线的编码器电路，并且接收机侧具有时钟和数据恢复电路17，时钟和数据恢复电路17从从时钟信号线，对所提取的信号进行解码以再现链接信息的解码器电路19以及基于时钟分量来调整低于1比特的歪斜的位歪斜电路21。

45. 发明授权

US07902860B2 Semiconductor circuit, and computing device and communications device using the same 有权
标题翻译：半导体电路，以及使用它的计算设备和通信设备
公开(公告)号：US07902860B2
公开(公告)日：2011-03-08
申请号：US12145829
申请日：2008-06-25
申请人： Keiichi Yamamoto , Norio Chujo , Toru Yazaki , Hisaaki Kanai
发明人： Keiichi Yamamoto , Norio Chujo , Toru Yazaki , Hisaaki Kanai
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03F3/3028 , H01L2924/19051 , H03F1/308 , H03F2200/447 , H03F2200/453 , H03K19/017581
摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.
摘要翻译：在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路计算由工作点计算电路找到的工作点处的阻抗。阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两个用于高侧和低侧阻抗调节。

46. 发明授权

US07816955B2 Ramp generator and circuit pattern inspection apparatus using the same ramp generator 有权
标题翻译：使用斜坡发生器的斜坡发生器和电路图案检查装置
公开(公告)号：US07816955B2
公开(公告)日：2010-10-19
申请号：US12044108
申请日：2008-03-07
申请人： Masayoshi Takahashi , Kengo Imagawa , Norio Chujo
发明人： Masayoshi Takahashi , Kengo Imagawa , Norio Chujo
IPC分类号： H03K4/06
CPC分类号： H03K4/06 , H01J37/1477 , H01J37/28 , H03K3/0231
摘要： The present invention provides a ramp generator capable of appropriately setting a rise starting point of an output voltage of a ramp waveform and an output voltage at the time of stable output. A current adjustment unit including a differential pair of transistors and an amplifier constitute a feedback circuit. By controlling the charging/discharging of an integration capacitor by ON/OFF of a discharge current source connected to a common emitter terminal of the current adjustment unit, an output of the ramp waveform outputted from an output terminal disposed at the connection end of the integration capacitor is controlled.
摘要翻译：本发明提供一种斜坡发生器，其能够适当地设定稳定输出时的斜坡波形的输出电压的上升起点和输出电压。包括差分对晶体管和放大器的电流调节单元构成反馈电路。通过连接到电流调节单元的公共发射极端子的放电电流源的ON / OFF来控制积分电容器的充电/放电，从设置在集成连接端的输出端子输出的斜坡波形的输出电容器被控制。

47. 发明授权

US07786751B2 Differential signaling system and method of controlling skew between signal lines thereof 有权
标题翻译：差分信号系统及其信号线之间的偏斜控制方法
公开(公告)号：US07786751B2
公开(公告)日：2010-08-31
申请号：US11831087
申请日：2007-07-31
申请人： Norio Chujo , Satoshi Muraoka
发明人： Norio Chujo , Satoshi Muraoka
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0272 , H01L24/45 , H01L24/46 , H01L2224/45565 , H01L2224/45572 , H01L2224/48092 , H01L2224/48137 , H01L2924/00011 , H01L2924/00014 , H01L2924/01015 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/43 , H01L2924/01006
摘要： The present invention provides a differential signaling system comprising: a driver circuit that transmits a differential signal; a receiver circuit that receives the differential signal; and two or more signal lines used for the differential signal to be transmitted by the driver circuit and received by the receiver circuit, wherein the driver circuit gives an arbitrary time lag between the two signals that form the differential signal before transmitting them.
摘要翻译：本发明提供一种差分信号系统，包括：发送差分信号的驱动电路; 接收差分信号的接收机电路; 并且用于差分信号的两条或更多条信号线由驱动器电路传输并由接收器电路接收，其中驱动器电路在发送差分信号之前形成差分信号的两个信号之间给出任意时滞。

48. 发明授权

US07772877B2 Output buffer circuit, differential output buffer circuit, output buffer circuit having regulation circuit and regulation function, and transmission method 有权
标题翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路及传输方式
公开(公告)号：US07772877B2
公开(公告)日：2010-08-10
申请号：US12343521
申请日：2008-12-24
申请人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
发明人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/028
摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, to improve resolution of a pre-emphasis amount without increasing power consumption or a circuit area. The output buffer includes a delay circuit, an inverter and output buffers to transmit a logical signal to a transmission line and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line. The output buffer has a selector and a variable resistance portion at an output resistance to change a pre-emphasis amount according to a change in a variable resistance value. The inverter is configured to select a signal to input into the output buffer, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
摘要翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，以提高预加重量的分辨率，而不增加功耗或电路面积。输出缓冲器包括延迟电路，反相器和输出缓冲器，以将逻辑信号传输到传输线，并根据传输线的信号衰减量产生在发送侧具有四种或更多种类型的信号电压的波形。输出缓冲器具有输出电阻的选择器和可变电阻部分，以根据可变电阻值的变化改变预加重量。逆变器被配置为选择要输入到输出缓冲器的信号，反转数据信号并通过选择器逻辑的选择信号调整抽头预加重量。

49. 发明授权

US07692445B2 Output buffer circuit and differential output buffer circuit, and transmission method 有权
标题翻译：输出缓冲电路和差分输出缓冲电路及其传输方式
公开(公告)号：US07692445B2
公开(公告)日：2010-04-06
申请号：US11686560
申请日：2007-03-15
申请人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/003
CPC分类号： H03K19/018521
摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.
摘要翻译：在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个选择器逻辑的选择信号。

50. 发明申请

US20090027867A1 High-speed signal transmission apparatus 有权
标题翻译：高速信号传输装置
公开(公告)号：US20090027867A1
公开(公告)日：2009-01-29
申请号：US12216737
申请日：2008-07-10
申请人： Keiichi Yamamoto , Norio Chujo , Takashi Kumakura , Yosuke Ishimatsu
发明人： Keiichi Yamamoto , Norio Chujo , Takashi Kumakura , Yosuke Ishimatsu
IPC分类号： H01R12/14
CPC分类号： H05K7/1458 , G06F1/185
摘要： A high-speed signal transmission apparatus comprises: a housing; a plurality of daughter boards juxtaposed to one another in the housing; board-side connectors each provided on corresponding each of the juxtaposed daughter boards; and cable-side connectors fixed in the housing; wherein each of the board-side connectors is insertable/removable into/from corresponding each of the cable-side connectors, and wherein a cable group whose impedance matching can be achieved makes connection between the predetermined cable-side connectors.
摘要翻译：高速信号传输装置包括：壳体; 多个子板在壳体中彼此并置; 每个并置的子板上设置的板侧连接器; 和固定在壳体中的电缆侧连接器; 其中每个电路板侧连接器可插入/移除相应的每个电缆侧连接器，并且其中可实现阻抗匹配的电缆组在预定电缆侧连接器之间进行连接。

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