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41. 发明申请

US20120204158A1 CONVERTER, SERVER SYSTEM, CONVERSION METHOD AND PROGRAM 失效
标题翻译：转换器，服务器系统，转换方法和程序
公开(公告)号：US20120204158A1
公开(公告)日：2012-08-09
申请号：US13363581
申请日：2012-02-01
申请人： Hideaki Komatsu , Moriyoshi Ohara
发明人： Hideaki Komatsu , Moriyoshi Ohara
IPC分类号： G06F9/44
CPC分类号： G06F9/541
摘要： A converter for converting an application program that is executed for every job request into a batch processing program for collectively processing a plurality of job requests. The converter includes: a code identifier for identifying a portion of the application program that includes a service request to another server, and a portion that does not include a service request; an integration unit for converting the service request into a collective service request that collectively issues a plurality of service requests corresponding to the plurality of job requests; a multiplexing unit for converting the processing code in the application program into a multiplexed code for executing multiple processings corresponding to the plurality of job requests; and an output unit for outputting, as the batch processing program, the application program that the integration unit and the multiplexing unit have processed.
摘要翻译： A转换器，用于将针对每个作业请求执行的应用程序转换成用于集体处理多个作业请求的批处理程序。该转换器包括：用于识别包括对另一服务器的服务请求的应用程序的一部分的代码标识符和不包括服务请求的部分; 集成单元，用于将服务请求转换为共同发出与多个作业请求对应的多个服务请求的集体服务请求; 复用单元，用于将应用程序中的处理代码转换为用于执行与多个作业请求相对应的多个处理的多路复用代码; 以及输出单元，用于作为批量处理程序输出积分单元和复用单元已经处理的应用程序。

42. 发明申请

US20110225225A1 METHOD, PROGRAM, AND SYSTEM FOR SOLVING ORDINARY DIFFERENTIAL EQUATION 审中-公开
标题翻译：用于解决普通差分方程的方法，程序和系统
公开(公告)号：US20110225225A1
公开(公告)日：2011-09-15
申请号：US13045866
申请日：2011-03-11
申请人： Arquimedes Martinez Canedo , Hideaki Komatsu , Takeo Yoshizawa
发明人： Arquimedes Martinez Canedo , Hideaki Komatsu , Takeo Yoshizawa
IPC分类号： G06G7/38
CPC分类号： G06F17/13
摘要： Each ordinary differential equation of simultaneous ordinary differential equations is solved with an embedded Runge-Kutta method. A difference Δ between an N-th order approximation and an (N+1)th order approximation is computed, and it is determined whether the difference is smaller than a predetermined threshold Δ0. If Δ≦Δ0, then a step size is determined using a predetermined computation formula containing Δ0/Δ, and then the process proceeds to next computation. A strand having an error of Δ>Δ0 is directed to execute recomputation using a step size calculated based on Δ0/Δ. Then the strand having the error executes recomputation by using a computed interpolated value. When the strand's error becomes smaller than the threshold Δ0 the strand reaches the same time step as the strands computing the other ordinary differential equations having no error. The process thereby proceeds to next computation of the whole simultaneous ordinary differential equations.
摘要翻译：利用嵌入式Runge-Kutta方法求解了每个常微分方程的常微分方程。差异与Dgr 计算N次近似和（N + 1）次近似之间的差，并且确定该差是否小于预定阈值＆Dgr; 0。如果＆Dgr;＆nlE;＆Dgr; 0，则使用包含＆Dgr; 0 /＆Dgr的预定计算公式来确定步长，然后处理进行到下一个计算。具有＆Dgr>＆Dgr; 0的错误的线用于使用基于＆Dgr; 0 /＆Dgr计算的步长来执行重新计算。然后，具有错误的线通过使用计算的内插值来执行重新计算。当线的误差变得小于阈值＆Dgr; 0时，股线达到与计算其他没有误差的其他普通微分方程相同的时间步长。该过程由此进行到整个同时的普通微分方程的下一次计算。

43. 发明授权

US07925471B2 Compiling method, apparatus, and program 失效
标题翻译：编译方法，装置和程序
公开(公告)号：US07925471B2
公开(公告)日：2011-04-12
申请号：US12190466
申请日：2008-08-12
申请人： Takuya Nakaike , Hideaki Komatsu
发明人： Takuya Nakaike , Hideaki Komatsu
IPC分类号： G05B13/02 , G05B13/00 , G06F19/00 , G06F17/40
CPC分类号： B25B21/00 , B25B21/026 , H04L67/02 , H04L67/322
摘要： Brings the response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining a response time goal which is a target value of the average response time; a section for calculating a predicted response time which is a predicted value of the average response time at the time point when a predetermined reference period has elapsed from setting an operation mode in the information processing apparatus, the operation mode being any of a plurality of operation modes which provide different throughputs; and a section for setting the operation mode in the information processing apparatus if predicted response time calculated by the predicted response time calculating section is less than goal.
摘要翻译：使Web服务器等的响应时间更接近目标值。控制由信息处理装置接收处理请求之间经过的平均响应时间和信息处理装置对处理请求的响应的控制器。控制器包括：用于获得作为平均响应时间的目标值的响应时间目标的部分; 用于计算预测响应时间的部分，所述预测响应时间是在从信息处理设备中的设置操作模式经过预定基准时段的时间点的平均响应时间的预测值，所述操作模式是多个操作提供不同吞吐量的模式; 以及如果由预测响应时间计算部计算出的预测响应时间小于目标，则在信息处理装置中设定操作模式的部分。

44. 发明申请

US20110060852A1 COMPUTER SYSTEM AND DATA TRANSFER METHOD THEREIN 审中-公开
标题翻译：计算机系统和数据传输方法
公开(公告)号：US20110060852A1
公开(公告)日：2011-03-10
申请号：US12874283
申请日：2010-09-02
申请人： Hideaki Komatsu , Fumitomo Ohsawa , Nobuaki Takahashi , Gang Zhang
发明人： Hideaki Komatsu , Fumitomo Ohsawa , Nobuaki Takahashi , Gang Zhang
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA transfer technique which can be adapted to “hardware in the loop simulation” (HILS) and which requires less overhead. In a computer system having a data transfer device, a continuous DMA mechanism successively and repeatedly outputs a data transfer request in response to an enable process. A simulation system for HILS places data as a result of the simulation in a predetermined area in a memory and transfers the data from the memory to the continuous DMA mechanism together with generation ID data. The continuous DMA mechanism stores the transferred generation ID as a received ID, and receives the transferred data in response to the event that the transferred generation ID differs from the received ID being stored. The continuous DMA mechanism successively repeats the data transfer request until it is disabled.
摘要翻译：一种DMA传输技术，可以适应“循环仿真中的硬件”（HILS），并且需要更少的开销。在具有数据传送装置的计算机系统中，连续的DMA机制响应于使能过程而连续并重复地输出数据传送请求。用于HILS的模拟系统将数据作为在存储器中的预定区域中的模拟的结果，并将数据与生成ID数据一起从存储器传送到连续DMA机制。连续DMA机制将传送的生成ID存储为接收到的ID，并且响应于所转移的生成ID与所接收的被存储的ID不同的事件接收传送的数据。连续DMA机制连续重复数据传输请求，直到禁用。

45. 发明授权

US07703095B2 Information processing and control 失效
标题翻译：信息处理和控制
公开(公告)号：US07703095B2
公开(公告)日：2010-04-20
申请号：US12171063
申请日：2008-07-10
申请人： Kiyokuni Kawachiya , Takeshi Ogasawara , Hideaki Komatsu
发明人： Kiyokuni Kawachiya , Takeshi Ogasawara , Hideaki Komatsu
IPC分类号： G06F9/46 , G06F9/45 , G06F11/34
CPC分类号： G06F9/46
摘要： Information processing apparatus, including occurrence number counter counting events that occurred in each of a plurality of CPUs. Apparatus performs functions of; storing accumulated occurrence number of events, which occurred while the thread is being executed by each of the CPUs, in a thread storage area of the thread associating accumulated occurrence number with CPU; storing, in the thread storage area, a value of occurrence number counter of the CPU, the value having been counted before the thread is resumed by the CPU; and adding, to accumulated occurrence number which has been stored in accumulated number storing unit while corresponding to the CPU, a difference value obtained by subtracting a counter value, which has been stored in the start-time number storing unit of the thread, from a counter value of the occurrence number counter of the CPU, in a case where the CPU terminates an execution of the thread.
摘要翻译：信息处理装置，包括在多个CPU中的每一个中发生的发生次数计数事件。仪器执行功能; 在所述线程关联累积发生次数与所述线程的线程存储区域中存储在所述CPU中执行所述线程时发生的事件的累计发生次数; 在线程存储区域中存储CPU的发生次数计数器的值，该值在CPU恢复线程之前已被计数; 并且对与CPU相对应地存储在累积数量存储单元中的累计发生次数相加，将从线程的开始时间数存储单元中存储的计数器值减去得到的差值从在CPU终止执行线程的情况下，CPU的发生次数计数器的计数值。

46. 发明申请

US20090306952A1 SIMULATION METHOD, SYSTEM AND PROGRAM 失效
标题翻译：模拟方法，系统和程序
公开(公告)号：US20090306952A1
公开(公告)日：2009-12-10
申请号：US12481105
申请日：2009-06-09
申请人： Koichi Kajitani , Hideaki Komatsu , Shuichi Shimizu
发明人： Koichi Kajitani , Hideaki Komatsu , Shuichi Shimizu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： In a normal operation, a physical unit simulator is allowed to speculatively perform high-speed continuous execution. Only when an actual input comes in, a speculative input and the actual input are compared with each other. Thereafter, in response to inconsistency between the inputs, the physical unit simulator is returned to a point closest to the point of the actual input and is allowed to execute a variable step module to reach the point of the actual input. Upon arrival at the point of the actual input, the simulator is shifted back to the high-speed continuous execution from there. Thus, a processing speed of the simulator can be significantly improved.
摘要翻译：在正常操作中，允许物理单元模拟器推测地执行高速连续执行。只有当实际输入进入时，推测输入和实际输入才能相互比较。此后，响应于输入之间的不一致，物理单元模拟器返回到最接近实际输入点的点，并允许执行可变步长模块以达到实际输入点。在到达实际输入点时，模拟器从那里转回高速连续执行。因此，可以显着地提高模拟器的处理速度。

47. 发明申请

US20080295108A1 Minimizing variations of waiting times of requests for services handled by a processor 失效
标题翻译：最小化处理器处理的服务请求的等待时间的变化
公开(公告)号：US20080295108A1
公开(公告)日：2008-11-27
申请号：US11753479
申请日：2007-05-24
申请人： Takeshi Ogasawara , Hideaki Komatsu
发明人： Takeshi Ogasawara , Hideaki Komatsu
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F11/3419 , G06F2201/88 , G06F2209/5018 , G06F2209/504 , G06F2209/508 , Y02D10/22
摘要： Variations of waiting times of requests for services handled by a processor are minimized. In response to the processor receiving a request for a service, an arrival time of the request for the service is recorded and added to a total arrival time for all requests for the service, and a counter of a number of waiting requests for the service is incremented. In response to the processor processing the request, the arrival time of the request is subtracted from the total arrival time, and the counter is decremented. In either case, an average waiting time of requests for the service is determined, a history of the average waiting times is maintained, and the variation within this history is determined. Where the variation is greater than a threshold, processor resources are adjusted to minimize variations within waiting times of requests for all the services handled by the processor.
摘要翻译：由处理器处理的服务请求的等待时间的变化被最小化。响应于处理器接收到对服务的请求，对服务请求的到达时间被记录并添加到对于服务的所有请求的总到达时间，并且对服务的等待请求的数量的计数器是递增响应于处理器处理请求，从总到达时间减去请求的到达时间，并且计数器递减。在任一情况下，确定服务请求的平均等待时间，维持平均等待时间的历史，并且确定该历史中的变化。在变化大于阈值的情况下，调整处理器资源以使处理器处理的所有服务的请求的等待时间内的变化最小化。

48. 发明申请

US20080134151A1 COMPILER REGISTER ALLOCATION AND COMPILATION 失效
标题翻译：编译器注册和编译
公开(公告)号：US20080134151A1
公开(公告)日：2008-06-05
申请号：US11927355
申请日：2007-10-29
申请人： Akira KOSEKI , Hideaki Komatsu
发明人： Akira KOSEKI , Hideaki Komatsu
IPC分类号： G06F9/44
CPC分类号： G06F8/441
摘要： Assigns suitable registers to a plurality of variables. A compiler converts a source program into instructions for a processor having: a simultaneously used variable acquisition section which obtains, with respect to each of a plurality of variables used in the source program, some of the other variables used simultaneously with the variable; an allocation sequence generation section which generates a plurality of allocation sequences between the plurality of variables to allocate each variable to one of the plurality of registers different from those to which some of the other variables used simultaneously with the variable are allocated; an allocation priority acquisition section which obtains allocation priorities indicating to which one of the plurality of registers each variable is allocated with priority; and a register allocation section which allocates the variables to registers in accordance with an allocation sequence selected on the basis of the allocation priorities.
摘要翻译：将适当的寄存器分配给多个变量。编译器将源程序转换为具有以下处理器的指令：具有：同时使用的变量获取部分，其针对源程序中使用的多个变量中的每一个获得与该变量同时使用的一些其它变量; 分配序列生成部，其生成所述多个变量之间的多个分配序列，以将每个变量分配给与所述变量同时使用的一些其他变量的多个寄存器中的一个不同的寄存器; 分配优先级获取部分，其优先级获得指示分配了多个寄存器中的每个变量的哪个寄存器的分配优先级; 以及寄存器分配部分，其根据基于分配优先级选择的分配序列将变量分配给寄存器。

49. 发明申请

US20080059955A1 COMPILING METHOD AND STORAGE MEDIUM THEREFOR 失效
标题翻译：编译方法和存储介质
公开(公告)号：US20080059955A1
公开(公告)日：2008-03-06
申请号：US11931300
申请日：2007-10-31
申请人： Akira Koseki , Mikio Takeuchi , Hideaki Komatsu
发明人： Akira Koseki , Mikio Takeuchi , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/447 , G06F8/441 , G06F8/443
摘要： A compiler includes a register allocator for allocating registers for instructions in a program to be compiled, and a code generator for generating object code based on the register allocation results performed by the register allocator. The register allocator allocates logical registers for instructions in the program to be compiled. The register allocation further allocates, to physical registers, the logical registers that are allocated to the instructions of the program, so that the physical registers that are live at a procedure call in the program to be compiled are allocated from the bottom of the register stack.
摘要翻译：编译器包括用于分配用于要编译的程序中的指令的寄存器的寄存器分配器，以及用于根据由寄存器分配器执行的寄存器分配结果来生成目标代码的代码生成器。寄存器分配器为要编译的程序中的指令分配逻辑寄存器。寄存器分配进一步向物理寄存器分配分配给程序指令的逻辑寄存器，以便在要编译的程序中的过程调用中存在的物理寄存器从寄存器堆栈的底部分配。

50. 发明申请

US20070156646A1 SYSTEM FOR PREFETCHING DATA NECESSARY TO EXECUTE PROGRAM FROM DATABASE 有权
标题翻译：用于从数据库执行程序的必要条件的系统
公开(公告)号：US20070156646A1
公开(公告)日：2007-07-05
申请号：US11608091
申请日：2006-12-07
申请人： Hideaki Komatsu , Akira Koseki , Toshio Suganuma
发明人： Hideaki Komatsu , Akira Koseki , Toshio Suganuma
IPC分类号： G06F17/30
CPC分类号： G06F17/3041 , G06F17/30471 , G06F17/30513 , Y10S707/99932 , Y10S707/99933
摘要： In order to improve the efficiency of execution of a program by prefetching data necessary to execute the program, a system is provided that causes a computer to execute a recursive query prior to a program being subjected to prefetching. This system detects from iterative processing in the program a query to generate a resultant table by selecting a record that satisfies a selection condition from a target table. The system generates an initial query to generate an initial table that includes values of variables that are set prior to starting the iterative processing in the program. Furthermore, the system generates a recursive query to generate the next intermediate table that is referred to in the next and later cycles of the iterative processing, in the recursive query corresponding to each cycle of the iterative processing that is sequentially performed, from an intermediate table that includes resultant tables generated by a target query in the preceding cycles of the iterative processing and the target table. Furthermore, the system generates a final query to generate a final table from the intermediate table sequentially generated by the recursive query.
摘要翻译：为了通过预取执行程序所必需的数据来提高程序的执行效率，提供了一种使得计算机在程序经受预取之前执行递归查询的系统。该系统通过从目标表中选择满足选择条件的记录来检测程序中的迭代处理查询以生成结果表。系统生成初始查询以生成初始表，其包括在开始程序中的迭代处理之前设置的变量值。此外，系统生成递归查询以生成在迭代处理的下一个和更后的循环中的递归查询中的下一个中间表，在递归查询中，对应于顺次执行的迭代处理的每个循环，从中间表其包括在迭代处理和目标表的前述循环中由目标查询生成的合成表。此外，系统生成最终查询以从递归查询依次生成的中间表生成最终表。

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