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41. 发明授权

US06438014B2 High speed access compatible memory module 有权
标题翻译：高速存取兼容内存模块
公开(公告)号：US06438014B2
公开(公告)日：2002-08-20
申请号：US09803148
申请日：2001-03-12
申请人： Seiji Funaba , Yoshinobu Nakagome , Masashi Horiguchi , Yoji Nishio
发明人： Seiji Funaba , Yoshinobu Nakagome , Masashi Horiguchi , Yoji Nishio
IPC分类号： G11C506
CPC分类号： G11C5/06 , G11C5/04 , G11C5/063 , H01L23/5387 , H01L25/065 , H01L25/0655 , H01L25/0657 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06579 , H01L2924/01055 , H01L2924/15312 , H01L2924/1532 , H01L2924/3011
摘要： A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each of the individual memory modules are connected in serial form, and each of the individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.
摘要翻译：模块基板具有与多个存储器芯片中的各个芯片数据端子相关联地分别设置的多个模块数据端子对，以及分别连接在多个模块数据端子对之间的多个模块数据布线。多个模块数据布线连接到它们对应的芯片数据终端，并被配置为可用作存储器访问数据总线。在并行布置多个存储器模块的存储器系统中，各个存储器模块的模块数据布线以串行形式连接，并且每个单独的模块数据配线不构成相对于数据的分支布线总线在内存系统的主板上。在存储器模块中，确保与存储器访问数据总线的宽度相对应的位数的并行访问。

42. 发明授权

US07760531B2 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US07760531B2
公开(公告)日：2010-07-20
申请号：US11511262
申请日：2006-08-29
申请人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
发明人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
IPC分类号： G11C5/02
CPC分类号： G11C5/147 , G11C5/02 , G11C7/02 , H01L24/48 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2924/00014 , H01L2924/10161 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor module includes a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device includes a first electrode. The second semiconductor device includes a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.
摘要翻译：半导体模块包括第一半导体器件，第二半导体器件和参考电压提供电路。第一半导体器件包括第一电极。第二半导体器件包括第二电极。参考电压提供电路用于向第一电极和第二电极提供参考电位，并用于抑制在第一电极和第二电极之间传递的噪声。

43. 发明申请

US20080040081A1 SIMULATION METHOD FOR IMPROVING FREEDOM OF SETTING PARAMETERS RELATING TO INPUT/OUTPUT CHARACTERISTICS OF A MEMORY CHIP 审中-公开
标题翻译：用于改进与存储芯片的输入/输出特性相关的设置参数自由的模拟方法
公开(公告)号：US20080040081A1
公开(公告)日：2008-02-14
申请号：US11676183
申请日：2007-02-16
申请人： Yoji NISHIO , Seiji Funaba , Yurika Aoki , Kazuyoshi Shoji , Koji Matsuo , Mariko Otsuka , Ryuichi Ikematsu , Sadahiro Nonoyama , Kae Fujii
发明人： Yoji NISHIO , Seiji Funaba , Yurika Aoki , Kazuyoshi Shoji , Koji Matsuo , Mariko Otsuka , Ryuichi Ikematsu , Sadahiro Nonoyama , Kae Fujii
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： In the simulation method of the present invention; one parameter is first selected from a plurality of parameters that relate to input/output characteristics. Next, regarding setting lines provided in a file for setting necessary choices from among a plurality of choices for a selected parameter, it is determined to either set choices by means of comment symbols that cause non-execution of the relevant lines, or set choices by means of identification codes, which are identifiers common to chips in which the same choice are to be set. When choices are to be set by means of comment symbols, the comment symbols of the setting lines of the necessary choices among the plurality of choices are deleted to make these setting lines effective. Alternatively, when choices are to be set by means of identification codes, the identification codes included in setting lines are rewritten to information for setting to the necessary choices. Finally, the simulation is executed.
摘要翻译：在本发明的模拟方法中，首先从与输入/输出特性相关的多个参数中选择一个参数。接下来，关于设置在文件中的设置线，用于从所选择的参数的多个选择中设置必要的选择，确定通过引起不执行相关行的注释符号设置选择，或者通过识别码的装置，它们是与要设置相同选择的芯片通用的标识符。当通过注释符号来设置选择时，删除多个选择中必要选择的设置行的注释符号，使得这些设置行成为有效。或者，当通过识别码设置选择时，将包括在设定线中的识别码重写为用于设置为必要选择的信息。最后，执行仿真。

44. 发明申请

US20070140040A1 MEMORY MODULE 失效
标题翻译：记忆模块
公开(公告)号：US20070140040A1
公开(公告)日：2007-06-21
申请号：US11611036
申请日：2006-12-14
申请人： Yurika Aoki , Seiji Funaba , Yoji Nishio
发明人： Yurika Aoki , Seiji Funaba , Yoji Nishio
IPC分类号： G11C5/06 , G11C8/00
CPC分类号： G11C5/063 , G11C5/04
摘要： A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.
摘要翻译：提供了具有多级配置的新型存储器模块，以解决由于输入到存储器的数据选通信号的定时偏离输入到其的时钟信号的定时的事实而无法进行高速操作的问题。在存储器模块中，在锁存环路电路的时钟信号输入引脚附近提供负载能力，其中输入时钟信号以使数据选通信号线的时间常数与时钟的时间常数相匹配信号线。时钟信号的输入定时和输入到存储器的数据选通信号的匹配使得存储器模块能够以高速运行。

45. 发明申请

US20070081376A1 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US20070081376A1
公开(公告)日：2007-04-12
申请号：US11634405
申请日：2006-12-06
申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
发明人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , G11C5/063 , G11C7/1048 , G11C11/4093 , G11C2207/105 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
摘要翻译：存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线孔（119）用于使线路循环。设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。该存储器模块通过连接器安装在其上提供存储器控制器的母板上。母线的有效特性阻抗与母板线路特性阻抗匹配。

46. 发明授权

US07016212B2 Memory module and memory system suitable for high speed operation 失效
标题翻译：内存模块和内存系统适合高速运行
公开(公告)号：US07016212B2
公开(公告)日：2006-03-21
申请号：US10630457
申请日：2003-07-29
申请人： Kayoko Shibata , Yoji Nishio , Seiji Funaba
发明人： Kayoko Shibata , Yoji Nishio , Seiji Funaba
IPC分类号： G11C5/06
CPC分类号： H05K1/0246 , H05K2201/10022 , H05K2201/10159
摘要： A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N−1)×Zeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N−1)×Zeffdimm/N2.
摘要翻译：存储器模块包括在引脚和总线的一端之间的尖端电阻器。多个存储器芯片在其两端之间连接到总线。终端电阻连接到总线的另一端。尖端电阻的阻抗Rs和终端电阻的终端电阻Rterm由下式给出：<？in-line-formula description =“In-line Formulas”end =“lead”？> Rs =（N-1）xZeffdimm / N和<？in-line-formula description =“In-line Formulas”end =“tail”？> <？in-line-formula description =“In-line Formulas”end =“lead”？> Rterm = Zeffdimm <？in-line-formula description =“在线公式”end =“tail”？>其中N表示存储器系统中的存储器模块的数量; 和Zeffdimm，由总线和存储器芯片组成的存储芯片布置部分的有效阻抗。在存储器系统中，存储器模块以连接方式连接到主板上的存储器控制器。主板的接线阻抗Zmb由下式给出：<？in-line-formula description =“In-line formula”end =“lead”？> Zmb =（2N-1）xZeffdimm / N < 。<？in-line-formula description =“In-line Formulas”end =“tail”？>

47. 发明授权

US06986072B2 Register capable of corresponding to wide frequency band and signal generating method using the same 有权
公开(公告)号：US06986072B2
公开(公告)日：2006-01-10
申请号：US10206822
申请日：2002-07-29
申请人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
发明人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
IPC分类号： G11C7/08 , G06F1/06 , G06F1/10
CPC分类号： G11C5/04 , G11C5/00 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/222 , H03L7/0814
摘要： A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

48. 发明授权

US06985009B2 Signal transmitting system 失效
标题翻译：信号传输系统
公开(公告)号：US06985009B2
公开(公告)日：2006-01-10
申请号：US10816187
申请日：2004-04-02
申请人： Yoji Nishio , Seiji Funaba
发明人： Yoji Nishio , Seiji Funaba
IPC分类号： H03K17/16
CPC分类号： H04L5/16 , G11C7/1006 , H04L25/0278
摘要： Semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected by a bidirectional bus which is a transmission line. A driver is of a push-pull type and a reception side is CTT-terminated. If a terminating resistor is in conformity with the characteristic impedance of the transmission line, the on resistance of the driver is equal to or lower than the characteristic impedance. If the on resistance of the driver is in conformity with the characteristic impedance of the transmission line, the value of the terminating resistor is equal to or lower than the characteristic impedance of the transmission line. If the reception side is VTT-terminated, the value of the VTT is ½ of a lower one of power supply voltages that are supplied to the respective semiconductor integrated circuit devices. The value of the terminating resistor is in conformity with the characteristic impedance of the transmission line. The semiconductor integrated circuit devices use a common reference voltage for determining the signal voltage.
摘要翻译：在不同电源电压下工作的半导体集成电路器件通过作为传输线的双向总线直接互连。驱动器是推挽式的，接收端是CTT端接的。如果终端电阻符合传输线的特性阻抗，则驱动器的导通电阻等于或低于特性阻抗。如果驱动器的导通电阻与传输线的特性阻抗一致，则终端电阻的值等于或低于传输线的特性阻抗。如果接收侧是VTT终止的，则VTT的值是提供给各个半导体集成电路器件的电源电压中的较低一个的1/2。终端电阻的值与传输线的特性阻抗一致。半导体集成电路器件使用公共参考电压来确定信号电压。

49. 发明授权

US06970369B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US06970369B2
公开(公告)日：2005-11-29
申请号：US10234261
申请日：2002-09-04
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G11C5/06 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/4093 , H03K19/0175 , D11C5/06
CPC分类号： G11C7/1048 , G11C5/063 , G11C7/10 , G11C11/4093
摘要： In a memory device having a controller and multiple memory modules both of which are mounted together on a motherboard, a high-speed operation is executed by suppressing waveform distortion caused by signal reflection. Since signal reflection occurs when a controller performs the writing/reading of data relative to memory units on memory modules, active terminator units are included in the controller and the memory units. These active terminator units are provided for a data bus and/or a clock bus in order to terminate these buses in memory units. The active terminator units provided for the controller and the memory units may be put into an inactive state when data is to be received.
摘要翻译：在具有控制器和多个存储器模块的存储器件中，两者都被安装在母板上，通过抑制由信号反射引起的波形失真来执行高速操作。由于当控制器执行相对于存储器模块上的存储器单元的数据的写入/读取时发生信号反射，因此主动终端单元包括在控制器和存储器单元中。这些有源终端单元被提供用于数据总线和/或时钟总线，以便在存储器单元中终止这些总线。当要接收数据时，为控制器和存储单元提供的有效终端单元可能会处于非活动状态。

50. 发明授权

US06707726B2 Register without restriction of number of mounted memory devices and memory module having the same 有权
标题翻译：在不限制安装的存储器件的数量和具有相同的存储器模块的情况下进行注册
公开(公告)号：US06707726B2
公开(公告)日：2004-03-16
申请号：US10206823
申请日：2002-07-29
申请人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
发明人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C2207/107
摘要： First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.
摘要翻译：第一和第二预处理触发器通过具有外部时钟信号的1/2的频率的时钟及其反时钟来锁存输入到寄存器的命令/地址信号。因此，命令/地址信号被分解成一组暂时具有两次的信号。例如，该组信号之一仅具有奇数命令/地址信号的数据内容，而另一个仅具有偶数个命令/地址信号的数据内容。由于该组信号具有两个命令/地址信号的周期，所以第一和第二后处理触发器可以根据由延迟锁定环电路产生的内部时钟信号来锁存信号，时间和保持时间充分确保。

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