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    • 42. 发明申请
    • Method and Apparatus for Plating Semiconductor Wafers
    • 用于电镀半导体晶片的方法和装置
    • US20100170803A1
    • 2010-07-08
    • US12724379
    • 2010-03-15
    • Yezdi DordiBob MaraschinJohn BoydFred C. RedekerCarl Woods
    • Yezdi DordiBob MaraschinJohn BoydFred C. RedekerCarl Woods
    • C25D7/12
    • C25D17/14C25D5/06C25D7/123C25D17/001C25D17/12H01L21/2885
    • First and second electrodes are disposed at first and second locations, respectively, proximate to a periphery of a wafer support, wherein the first and second location are substantially opposed to each other relative to the wafer support. Each of the first and second electrodes can be moved to electrically connect with and disconnect from a wafer held by the wafer support. An anode is disposed over and proximate to the wafer such that a meniscus of electroplating solution is maintained between the anode and the wafer. As the anode moves over the wafer from the first location to the second location, an electric current is applied through the meniscus between the anode and the wafer. Also, as the anode is moved over the wafer, the first and second electrodes are controlled to connect with the wafer while ensuring that the anode does not pass over an electrode that is connected.
    • 第一和第二电极分别设置在靠近晶片支撑件的周边的第一和第二位置处,其中第一和第二位置相对于晶片支撑件彼此基本相对。 可以使第一和第二电极中的每一个移动以与由晶片支撑件保持的晶片电连接和断开。 阳极设置在晶片上方并且靠近晶片,使得电镀溶液的弯液面保持在阳极和晶片之间。 当阳极从晶片从第一位置移动到第二位置时,通过阳极和晶片之间的弯液面施加电流。 此外,当阳极移动到晶片上时,第一和第二电极被控制以与晶片连接,同时确保阳极不通过连接的电极。
    • 43. 发明授权
    • Method and apparatus for plating semiconductor wafers
    • 用于电镀半导体晶片的方法和装置
    • US07704367B2
    • 2010-04-27
    • US10879263
    • 2004-06-28
    • Yezdi DordiBob MaraschinJohn BoydFred C. RedekerCarl Woods
    • Yezdi DordiBob MaraschinJohn BoydFred C. RedekerCarl Woods
    • C25D7/12H01L21/288B23H7/26C25B11/00
    • C25D17/14C25D5/06C25D7/123C25D17/001C25D17/12H01L21/2885
    • First and second electrodes are disposed at first and second locations, respectively, proximate to a periphery of a wafer support, wherein the first and second location are substantially opposed to each other relative to the wafer support. Each of the first and second electrodes can be moved to electrically connect with and disconnect from a wafer held by the wafer support. An anode is disposed over and proximate to the wafer such that a meniscus of electroplating solution is maintained between the anode and the wafer. As the anode moves over the wafer from the first location to the second location, an electric current is applied through the meniscus between the anode and the wafer. Also, as the anode is moved over the wafer, the first and second electrodes are controlled to connect with the wafer while ensuring that the anode does not pass over an electrode that is connected.
    • 第一和第二电极分别设置在靠近晶片支撑件的周边的第一和第二位置处,其中第一和第二位置相对于晶片支撑件彼此基本相对。 可以使第一和第二电极中的每一个移动以与由晶片支撑件保持的晶片电连接和断开。 阳极设置在晶片上方并且靠近晶片,使得电镀溶液的弯液面保持在阳极和晶片之间。 当阳极从晶片从第一位置移动到第二位置时,通过阳极和晶片之间的弯液面施加电流。 此外,当阳极移动到晶片上时,第一和第二电极被控制以与晶片连接,同时确保阳极不通过连接的电极。
    • 45. 发明授权
    • Method and apparatus for semiconductor wafer planarization
    • 用于半导体晶片平面化的方法和装置
    • US07368017B2
    • 2008-05-06
    • US10734704
    • 2003-12-12
    • Fred C. RedekerJohn BoydYezdi DordiWilliam ThieBob Maraschin
    • Fred C. RedekerJohn BoydYezdi DordiWilliam ThieBob Maraschin
    • B05C3/02
    • H01L21/7684C23C18/06C23C18/1216C23C18/1225C23C18/1291C23C18/14H01L21/288
    • Broadly speaking, the present invention provides a method and an apparatus for planarizing a semiconductor wafer (“wafer”). More specifically, the present invention provides for depositing a planarizing layer over the wafer, wherein the planarizing layer serves to fill recessed areas present on a surface of the wafer. A planar member is positioned over and proximate to a top surface of the wafer. Positioning of the planar member serves to entrap electroless plating solution between the planar member and the wafer surface. Radiant energy is applied to the wafer surface to cause a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase in turn causes plating reactions to occur at the wafer surface. Material deposited through the plating reactions forms a planarizing layer that conforms to a planarity of the planar member.
    • 广义而言,本发明提供了一种用于平面化半导体晶片(“晶片”)的方法和装置。 更具体地,本发明提供了在晶片上沉积平坦化层,其中平坦化层用于填充存在于晶片表面上的凹陷区域。 平面构件定位在晶片的顶表面上方并靠近晶片的顶表面。 平面构件的定位用于在平面构件和晶片表面之间夹带化学镀溶液。 辐射能量被施加到晶片表面以在晶片表面和化学镀溶液之间的界面处引起温度升高。 温度升高又会导致电镀反应发生在晶片表面。 通过电镀反应沉积的材料形成符合平面构件平坦度的平坦化层。
    • 46. 发明授权
    • Method and apparatus to form a planarized Cu interconnect layer using electroless membrane deposition
    • 使用无电沉积膜形成平坦化Cu互连层的方法和装置
    • US06864181B2
    • 2005-03-08
    • US10402600
    • 2003-03-27
    • Fred C. RedekerJohn Boyd
    • Fred C. RedekerJohn Boyd
    • H01L21/288H01L21/768H01L21/311C03C15/00H01L23/48
    • H01L21/288H01L21/7684
    • A planarized conductive material is formed over a substrate including narrow and wide features. The conductive material is formed through a succession of deposition processes. A first deposition process forms a first layer of the conductive material that fills the narrow features and at least partially fills the wide features. A second deposition process forms a second layer of the conductive material within cavities in the first layer. A flexible material can reduce a thickness of the first layer above the substrate while delivering a solution to the cavities to form the second layer therein. The flexible material can be a porous membrane attached to a pressurizable reservoir filled with the solution. The flexible material can also be a poromeric material wetted with the solution.
    • 在包括窄和宽的特征的衬底上形成平坦化的导电材料。 导电材料通过一系列沉积工艺形成。 第一沉积工艺形成导电材料的第一层,其填充窄特征并且至少部分地填充宽的特征。 第二沉积工艺在第一层的空腔内形成导电材料的第二层。 柔性材料可以减小衬底之上的第一层的厚度,同时将溶液递送到空腔以在其中形成第二层。 柔性材料可以是连接到填充有溶液的可加压储存器的多孔膜。 柔性材料也可以是用溶液润湿的多孔体材料。