专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07414917B2 Re-driving CAwD and rD signal lines 失效
标题翻译：重新启动CAwD和rD信号线
公开(公告)号：US07414917B2
公开(公告)日：2008-08-19
申请号：US11192335
申请日：2005-07-29
申请人： Hermann Ruckerbauer , Simon Muff , Christian Weiss , Peter Gregorius
发明人： Hermann Ruckerbauer , Simon Muff , Christian Weiss , Peter Gregorius
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/06 , H05K1/142
摘要： Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.
摘要翻译：本文描述了使用其的半导体存储器模块和半导体存储器系统。这些模块将常规DIMM分成一系列独立的较小内存模块。每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。

42. 发明授权

US07180821B2 Memory device, memory controller and memory system having bidirectional clock lines 有权
标题翻译：存储器件，存储器控制器和具有双向时钟线的存储器系统
公开(公告)号：US07180821B2
公开(公告)日：2007-02-20
申请号：US10954869
申请日：2004-09-30
申请人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C5/04 , G11C7/22 , G11C7/225
摘要： One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.
摘要翻译：本发明的一个实施例提供了一种适于根据写时钟信号接收数据并根据读时钟信号输出数据的存储器件，包括配置成输出读时钟信号并接收写时钟信号的时钟端口以及串行双向驱动器，被配置为经由时钟端口输出读取时钟信号，并经由时钟端口同时接收写时钟信号。

43. 发明申请

US20060112230A1 Integrated memory device and memory module 审中-公开
标题翻译：集成存储器件和存储器模块
公开(公告)号：US20060112230A1
公开(公告)日：2006-05-25
申请号：US10996956
申请日：2004-11-24
申请人： Christian Sichert , Hermann Ruckerbauer , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Christian Sichert , Hermann Ruckerbauer , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： The present invention relates to an integrated memory device including: memory cells arranged at wordlines and bitlines, wherein the memory cells are addressable in sets of 2n bit, wherein n is an integer, a pre-fetch read unit to pre-fetch an addressed set of 2n data bit in parallel from the addressed memory area, buffer memory to buffer the number of pre-fetched data bits; a number m of output ports to output the data bits buffered in the buffer memory; an output controller for controlling the outputting of the data bits buffered in the buffer memory to the number m of output ports in groups of m bits in one or a plurality of successive cycles, characterized in that the number m of output ports is different to any of the possible numbers 2n of the sets of addressable memory cells.
摘要翻译：本发明涉及一种集成存储器件，其包括：以字线和位线布置的存储器单元，其中存储器单元可以以2位为单位的集合寻址，其中n是整数，预取读取单元，用于从寻址的存储器区域缓冲存储器并行地预取寻址的2 数据位组，以缓冲预取数据位的数量; 多个输出端口输出缓冲存储器中缓冲的数据位; 输出控制器，用于在一个或多个连续循环中控制以缓冲存储器缓冲的数据位输出到m位组的输出端口的数量m，其特征在于，输出端口的数量m不同于任何的可寻址存储器单元组的可能数字2 。

44. 发明申请

US20060067156A1 Memory device, memory controller and memory system having bidirectional clock lines 有权
标题翻译：具有双向时钟线的存储器件，存储器控制器和存储器系统
公开(公告)号：US20060067156A1
公开(公告)日：2006-03-30
申请号：US10954869
申请日：2004-09-30
申请人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C5/04 , G11C7/22 , G11C7/225
摘要： One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.
摘要翻译：本发明的一个实施例提供了一种适于根据写时钟信号接收数据并根据读时钟信号输出数据的存储器件，包括配置成输出读时钟信号并接收写时钟信号的时钟端口以及串行双向驱动器，被配置为经由时钟端口输出读取时钟信号，并经由时钟端口同时接收写时钟信号。

45. 发明授权

US07334150B2 Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals 有权
标题翻译：具有时钟信号再生电路的存储器模块和用于临时存储输入命令和地址信号的寄存器电路
公开(公告)号：US07334150B2
公开(公告)日：2008-02-19
申请号：US11002148
申请日：2004-12-03
申请人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G06F1/04
CPC分类号： G11C5/04 , G11C5/063
摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.
摘要翻译：半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。

46. 发明申请

US20070079057A1 Semiconductor memory system and memory module 审中-公开
标题翻译：半导体存储器系统和存储器模块
公开(公告)号：US20070079057A1
公开(公告)日：2007-04-05
申请号：US11239829
申请日：2005-09-30
申请人： Hermann Ruckerbauer , Peter Gregorius
发明人： Hermann Ruckerbauer , Peter Gregorius
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1673 , G06F13/1684
摘要： A semiconductor memory system is disclosed. In one embodiment, the semiconductor memory system and memory module of the present invention provides a buffer, wherein at least one write buffer chip on the memory module is only buffering and registering write data, command and address signals written from a memory controller to the memory chips. As read data are written back from each memory chip directly to the memory controller through unidirectional point-to-point read data lines the present semiconductor memory system achieves a low latency as compared with a fully buffered DIMM concept. As read data are only unidirectional a high transmission bandwidth can be achieved.
摘要翻译：公开了半导体存储器系统。在一个实施例中，本发明的半导体存储器系统和存储器模块提供了缓冲器，其中存储器模块上的至少一个写入缓冲器芯片仅缓冲并将从存储器控制器写入的写数据，命令和地址信号注册到存储器筹码由于读取数据通过单向点对点读取数据线直接从每个存储器芯片写回存储器控制器，与全缓冲DIMM概念相比，本半导体存储器系统实现了低延迟。由于读取数据只是单向的，所以可以实现高传输带宽。

47. 发明申请

US20060291263A1 Memory system and method of accessing memory chips of a memory system 失效
标题翻译：存储器系统和访问存储器系统的存储器芯片的方法
公开(公告)号：US20060291263A1
公开(公告)日：2006-12-28
申请号：US11128789
申请日：2005-05-13
申请人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
发明人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.
摘要翻译：公开了一种存储器系统和方法。在一个实施例中，存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线被布置在分别指定的拓扑中。连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。

48. 发明申请

US20060104132A1 SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR THE TRANSFER OF WRITE AND READ DATA SIGNALS IN A SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：用于半导体存储器系统中写入和读取数据信号的半导体存储器系统和方法
公开(公告)号：US20060104132A1
公开(公告)日：2006-05-18
申请号：US10986767
申请日：2004-11-15
申请人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1018
摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.
摘要翻译：用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串具体的突发长度。该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。

49. 发明申请

US20070195505A1 Memory module device 审中-公开
标题翻译：内存模块设备
公开(公告)号：US20070195505A1
公开(公告)日：2007-08-23
申请号：US11357413
申请日：2006-02-21
申请人： Dominique Savignac , Peter Gregorius , Hermann Ruckerbauer , Simon Muff
发明人： Dominique Savignac , Peter Gregorius , Hermann Ruckerbauer , Simon Muff
IPC分类号： H05K7/20
CPC分类号： H05K1/183 , G11C5/02 , G11C5/025 , G11C5/04 , H01L23/552 , H01L24/73 , H01L25/18 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2924/01019 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/16195 , H01L2924/16251 , H01L2924/19107 , H01L2924/3025 , H05K1/181 , H05K2201/10159 , H05K2201/10515 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A memory module device includes a printed circuit board, a plurality of memory modules and a buffer module. Lines are provided in or on the printed circuit board to connect the buffer module to the memory modules. The memory modules are combined at least partially to form memory module stacks.
摘要翻译：存储器模块装置包括印刷电路板，多个存储器模块和缓冲模块。在印刷电路板中或印刷电路板上提供线路，以将缓冲模块连接到存储器模块。存储器模块至少部分地组合以形成存储器模块堆栈。

50. 发明申请

US20070057695A1 Semiconductor memory chip with re-drive unit for electrical signals 审中-公开
标题翻译：半导体存储芯片，带有重新驱动单元的电信号
公开(公告)号：US20070057695A1
公开(公告)日：2007-03-15
申请号：US11226456
申请日：2005-09-15
申请人： Hermann Ruckerbauer , Peter Gregorius
发明人： Hermann Ruckerbauer , Peter Gregorius
IPC分类号： H03K19/0175
CPC分类号： G11C11/4096 , G06F13/4077 , G11C7/1066
摘要： A semiconductor memory chip includes a re-drive unit for re-driving electrical signals to at least one semiconductor memory chip connected thereto. The re-drive unit includes a direct line connection between two connecting nodes, i.e., one input terminal and one output terminal of the semiconductor memory chip.
摘要翻译：半导体存储器芯片包括用于将电信号重新驱动到连接到其上的至少一个半导体存储器芯片的重新驱动单元。重新驱动单元包括两个连接节点之间的直接线路连接，即半导体存储器芯片的一个输入端子和一个输出端子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式