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41. 发明授权

US07834652B1 Method and devices for storing a security key using programmable fuses 有权
标题翻译：使用可编程保险丝存储安全密钥的方法和设备
公开(公告)号：US07834652B1
公开(公告)日：2010-11-16
申请号：US12709685
申请日：2010-02-22
申请人： Howard Tang , Ju Shen , San-Ta Kow
发明人： Howard Tang , Ju Shen , San-Ta Kow
IPC分类号： H03K19/00
CPC分类号： H03K19/17768 , G06F21/76
摘要： In embodiment of the invention, a programmable logic device includes configuration memory adapted to be programmed with configuration data and a plurality of programmable fuses adapted to store a security key for use with configuration data. The security key includes a plurality of data bit values, wherein each data bit value of the security key is associated with a subset of a least three fuses each storing a bit. Each of a plurality of decoders is adapted to retrieve a data bit value of the security key by providing the bit value stored by a majority of the fuses of the associated subset as the data bit value of the security key.
摘要翻译：在本发明的实施例中，可编程逻辑器件包括适于用配置数据编程的配置存储器和适于存储与配置数据一起使用的安全密钥的多个可编程保险丝。安全密钥包括多个数据比特值，其中安全密钥的每个数据比特值与每个存储一位的至少三个熔丝的子集相关联。多个解码器中的每一个适于通过提供由相关联的子集的大多数熔丝存储的位值作为安全密钥的数据位值来检索安全密钥的数据位值。

42. 发明授权

US07768300B1 Programmable logic device providing serial peripheral interfaces 有权
标题翻译：提供串行外设接口的可编程逻辑器件
公开(公告)号：US07768300B1
公开(公告)日：2010-08-03
申请号：US12511388
申请日：2009-07-29
申请人： Howard Tang , Roger Spinti , San-Ta Kow
发明人： Howard Tang , Roger Spinti , San-Ta Kow
IPC分类号： H03K19/177 , G11C8/00
CPC分类号： H03K19/17776 , H03K19/17744 , H03K19/17748 , H03K19/17756
摘要： In one embodiment, a programmable logic device (PLD) includes a slave port and a master port. The slave port can receive a configuration data bitstream and a slave clock signal from a master port of a first external device. The master port can provide the configuration data bitstream and a master clock signal from the PLD to a slave port of a second external device. An interface block in the PLD can pass the configuration data bitstream from the slave port through the PLD to the master port. In another embodiment, a PLD includes a slave serial peripheral interface (SPI) port and configuration memory. The slave SPI port can receive a configuration data bitstream and a slave clock signal from a master SPI port of an external device. The configuration memory stores the received bitstream for configuring the PLD.
摘要翻译：在一个实施例中，可编程逻辑器件（PLD）包括从端口和主端口。从端口可以从第一外部设备的主端口接收配置数据比特流和从时钟信号。主端口可以将配置数据比特流和来自PLD的主时钟信号提供给第二外部设备的从端口。 PLD中的接口块可以将配置数据比特流从从端口通过PLD传递到主端口。在另一个实施例中，PLD包括从串行外设接口（SPI）端口和配置存储器。从站SPI端口可以从外部设备的主SPI端口接收配置数据位流和从时钟信号。配置存储器存储用于配置PLD的接收比特流。

43. 发明授权

US07702977B1 Programmable logic devices with custom identification systems and methods 有权
标题翻译：具有自定义识别系统和方法的可编程逻辑器件
公开(公告)号：US07702977B1
公开(公告)日：2010-04-20
申请号：US12480565
申请日：2009-06-08
申请人： Howard Tang , Om P. Agrawal , Fabiano Fontana
发明人： Howard Tang , Om P. Agrawal , Fabiano Fontana
IPC分类号： G01R31/28 , G06F21/00
CPC分类号： G06F21/76
摘要： In one embodiment, a programmable logic device includes a first multiplexer; a first memory adapted to store an identification code of the programmable logic device; and a second memory adapted to store an identification code of the programmable logic device. Inputs of a second multiplexer are coupled to the first memory and the second memory, and an output of the multiplexer is coupled to an input of the first multiplexer. The second multiplexer is adapted to select between the identification code stored in the first memory and the identification code stored in the second memory to provide the selected identification code to the first multiplexer.
摘要翻译：在一个实施例中，可编程逻辑器件包括第一多路复用器; 适于存储可编程逻辑器件的识别码的第一存储器; 以及适于存储可编程逻辑器件的识别码的第二存储器。第二多路复用器的输入耦合到第一存储器和第二存储器，并且多路复用器的输出耦合到第一多路复用器的输入端。第二多路复用器适于在存储在第一存储器中的识别码与存储在第二存储器中的识别码之间进行选择，以将所选择的识别码提供给第一多路复用器。

44. 发明授权

US07675313B1 Methods and systems for storing a security key using programmable fuses 有权
标题翻译：使用可编程保险丝存储安全密钥的方法和系统
公开(公告)号：US07675313B1
公开(公告)日：2010-03-09
申请号：US11498645
申请日：2006-08-03
申请人： Howard Tang , Ju Shen , San-Ta Kow
发明人： Howard Tang , Ju Shen , San-Ta Kow
IPC分类号： H03K19/00
CPC分类号： H03K19/17768 , G06F21/76
摘要： Systems and methods are disclosed herein to provide improved security key techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a method of providing data security for a programmable logic device (PLD) includes programming a plurality of programmable fuses that stores a security key comprising a plurality of data bit values, wherein each data bit value is associated with a respective subset of at least three of the fuses. The security key is retrieved from the fuses using the data bit values stored by each subset of the fuses. An encrypted configuration data bitstream is decrypted using the retrieved security key to obtain an original configuration data bitstream to configure the PLD.
摘要翻译：本文公开了系统和方法，以提供用于可编程逻辑器件的改进的安全关键技术。例如，根据本发明的实施例，一种为可编程逻辑器件（PLD）提供数据安全性的方法包括对存储包括多个数据位值的安全密钥的多个可编程熔丝进行编程，其中每个数据位值与至少三个保险丝的相应子集相关联。使用保险丝的每个子集存储的数据位值，从保险丝检索安全密钥。使用所检索的安全密钥解密加密的配置数据比特流，以获得配置PLD的原始配置数据比特流。

45. 发明授权

US07546498B1 Programmable logic devices with custom identification systems and methods 有权
标题翻译：具有自定义识别系统和方法的可编程逻辑器件
公开(公告)号：US07546498B1
公开(公告)日：2009-06-09
申请号：US11446308
申请日：2006-06-02
申请人： Howard Tang , Om P. Agrawal , Fabiano Fontana
发明人： Howard Tang , Om P. Agrawal , Fabiano Fontana
IPC分类号： G01R31/28 , G06F21/00
CPC分类号： G06F21/76
摘要： Systems and methods are disclosed herein to provide techniques for providing programmable identification codes (IDCODE) for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first non-volatile memory adapted to store a first identification code of the programmable logic device, and a second memory adapted to store a second identification code of the programmable logic device. A control circuit selects between the first identification code stored in the first non-volatile memory and the second identification code stored in the second memory to provide as an identification code for the programmable logic device.
摘要翻译：本文公开了提供用于为PLD提供可编程识别码（IDCODE）的技术的系统和方法。例如，根据本发明的实施例，可编程逻辑器件包括适于存储可编程逻辑器件的第一识别码的第一非易失性存储器，以及适于存储可编程逻辑器件的第二识别码的第二存储器可编程逻辑器件。控制电路在存储在第一非易失性存储器中的第一识别码与存储在第二存储器中的第二识别码之间进行选择，以提供可编程逻辑器件的识别码。

46. 发明授权

US07495970B1 Flexible memory architectures for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的灵活存储器架构
公开(公告)号：US07495970B1
公开(公告)日：2009-02-24
申请号：US11446309
申请日：2006-06-02
申请人： Howard Tang , Fabiano Fontana , David L. Rutledge , Om P. Agrawal , Henry Law
发明人： Howard Tang , Fabiano Fontana , David L. Rutledge , Om P. Agrawal , Henry Law
IPC分类号： G11C7/10
CPC分类号： H03K19/17772 , G11C29/028 , H03K19/1776
摘要： Systems and methods provide non-volatile memory architectures for programmable logic devices. For example, a programmable logic device may include logic blocks, input/output blocks, and configuration memory to store configuration data for configuration of the logic blocks and the input/output blocks. A first non-volatile memory may store user information, besides configuration data, and a first port includes a dedicated serial peripheral interface to provide access to the first non-volatile memory.
摘要翻译：系统和方法为可编程逻辑器件提供非易失性存储器架构。例如，可编程逻辑器件可以包括逻辑块，输入/输出块和配置存储器，以存储用于配置逻辑块和输入/输出块的配置数据。除了配置数据之外，第一非易失性存储器可以存储用户信息，并且第一端口包括用于提供对第一非易失性存储器的访问的专用串行外围接口。

47. 发明授权

US07375549B1 Reconfiguration of programmable logic devices 有权
标题翻译：可编程逻辑器件的重新配置
公开(公告)号：US07375549B1
公开(公告)日：2008-05-20
申请号：US11350436
申请日：2006-02-09
申请人： Howard Tang , Ju Shen , San-Ta Kow
发明人： Howard Tang , Ju Shen , San-Ta Kow
IPC分类号： H03K19/173
CPC分类号： H03K19/17772 , H03K19/17744 , H03K19/17764
摘要： Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks and corresponding input/output pins, and a plurality of configuration memory cells. The configuration memory cells are adapted to store configuration data for configuration of the logic blocks and the input/output blocks. A data port is adapted to provide a clock signal to and receive configuration data from an external memory. A plurality of circuits are adapted to hold the input/output pins in a known logic state during the configuration.
摘要翻译：为可编程逻辑器件（PLD）提供了改进的重新配置技术。例如，根据本发明的实施例，可编程逻辑器件包括多个逻辑块，多个输入/输出块和相应的输入/输出引脚以及多个配置存储器单元。配置存储单元适于存储用于配置逻辑块和输入/输出块的配置数据。数据端口适于向外部存储器提供时钟信号并从外部存储器接收配置数据。多个电路适于在配置期间将输入/输出引脚保持在已知的逻辑状态。

48. 发明授权

US07088132B1 Configuring FPGAs and the like using one or more serial memory devices 有权
标题翻译：使用一个或多个串行存储设备配置FPGA等
公开(公告)号：US07088132B1
公开(公告)日：2006-08-08
申请号：US11243255
申请日：2005-10-04
申请人： Howard Tang , Satwant Singh , Ann Wu
发明人： Howard Tang , Satwant Singh , Ann Wu
IPC分类号： H03K19/177
CPC分类号： H03K19/17776 , H03K19/17744 , H03K19/17748
摘要： The configuration architecture for a programmable device, such as an FPGA, includes one or more memory devices connected directly to the FPGA such that the FPGA can be configured with configuration data stored in the memory devices without transmitting the configuration data via a controller connected between any of the memory devices and the FPGA. In one embodiment, the FPGA has an Serial Peripheral Interface (SPI) that is connected to the SPI interface of each of one or more SPI serial flash PROMs operating as boot PROMs. When there are two or more boot PROMs, each PROM stores a portion of the FPGA's configuration data and the FPGA interleaves the data from multiple boot PROMs to generate a serial configuration data bitstream. The present invention enables boot PROMs having different sizes and/or storing different amounts of configuration data to be simultaneously connected to an FPGA to support efficient configuration architectures.
摘要翻译：用于可编程器件（例如FPGA）的配置架构包括直接连接到FPGA的一个或多个存储器件，使得FPGA可配置存储在存储器件中的配置数据，而不通过连接在任何的存储器件和FPGA。在一个实施例中，FPGA具有串行外设接口（SPI），其连接到作为引导PROM操作的一个或多个SPI串行闪存PROM中的每一个的SPI接口。当存在两个或更多个引导PROM时，每个PROM存储FPGA配置数据的一部分，并且FPGA交互来自多个引导PROM的数据以生成串行配置数据比特流。本发明使得具有不同尺寸和/或存储不同数量的配置数据的引导PROM能够同时连接到FPGA以支持有效的配置架构。

49. 发明授权

US07081771B2 Upgradeable and reconfigurable programmable logic device 有权
公开(公告)号：US07081771B2
公开(公告)日：2006-07-25
申请号：US10783886
申请日：2004-02-20
申请人： Om P. Agrawal , Howard Tang , Jack Wong
发明人： Om P. Agrawal , Howard Tang , Jack Wong
IPC分类号： H03K19/177
CPC分类号： H03K19/17772 , H03K19/17732 , H03K19/1776 , H03K19/17768
摘要： Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.

50. 发明授权

US5329179A Arrangement for parallel programming of in-system programmable IC logical devices 失效
标题翻译：系统可编程IC逻辑器件的并行编程布置
公开(公告)号：US5329179A
公开(公告)日：1994-07-12
申请号：US957311
申请日：1992-10-05
申请人： Howard Tang , Cyrus Tsui
发明人： Howard Tang , Cyrus Tsui
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054
摘要： A plurality of programmable logic devices are connected in parallel to a programming command generator. A device selector connects individual devices with the programming command generator, thereby permitting the individual devices to be programmed without routing the programming data through other devices. In an alternative embodiment, an identification code is used to place the individual device in a condition to receive programming data. Using the teachings of this invention, programming data may initially be entered into a plurality of devices, and then the data entered in all the devices may be used to program the devices simultaneously. This procedure requires less time than entering data and giving each device the execute command in sequence.
摘要翻译：多个可编程逻辑器件并行连接到编程命令发生器。设备选择器将各个设备与编程命令发生器连接，从而允许编程各个设备，而不通过其他设备路由编程数据。在替代实施例中，使用识别码将单个设备置于接收节目数据的状态。使用本发明的教导，编程数据可以最初被输入到多个设备中，然后可以使用在所有设备中输入的数据来同时对设备进行编程。该过程比输入数据需要更少的时间，并且每个设备按顺序给出执行命令。

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