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41. 发明授权

US06200865B1 Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate 有权
标题翻译：使用牺牲介电结构形成具有自对准阈值的半导体器件调整并覆盖低电阻栅极
公开(公告)号：US06200865B1
公开(公告)日：2001-03-13
申请号：US09205443
申请日：1998-12-04
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21336
CPC分类号： H01L29/66537 , H01L21/28273 , H01L29/42324 , H01L29/66545 , H01L29/6659 , H01L29/66825
摘要： A semiconductor device is provided and formed using self-aligned low-resistance gates within a metal-oxide semiconductor (MOS) process. A sacrificial dielectric gate structure is formed on a semiconductor substrate instead of a conventional gate dielectric/gate conductor stack. After forming junction regions within a semiconductor substrate, the gate structure is removed to form a trench within a dielectric formed above the substrate. A low-resistance gate material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The gate material can take various forms, including a single layer or multiple metal and/or dielectric layers interposed throughout the as-filled trench. The gate formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.
摘要翻译：在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻栅极提供并形成半导体器件。在半导体衬底上形成牺牲电介质栅极结构，而不是传统的栅极介质/栅极导体堆叠。在半导体衬底中形成结区之后，去除栅极结构，以在衬底之上形成的电介质内形成沟槽。然后可以在沟槽内，即在去除栅极导体的区域中布置低电阻栅极材料。栅极材料可以采取各种形式，包括插入整个填充沟槽中的单层或多个金属和/或介电层。栅极形成发生在高温循环之后，通常与激活以前注入的结或生长的栅极电介质相关联。因此，可以使用诸如铜或铜合金的低温金属。

42. 发明授权

US06191446B1 Formation and control of a vertically oriented transistor channel length 失效
标题翻译：垂直取向晶体管沟道长度的形成和控制
公开(公告)号：US06191446B1
公开(公告)日：2001-02-20
申请号：US09035780
申请日：1998-03-04
申请人： Mark I. Gardner , John J. Bush , Jon D. Cheek
发明人： Mark I. Gardner , John J. Bush , Jon D. Cheek
IPC分类号： H01L2976
CPC分类号： H01L29/66666 , H01L29/665 , H01L29/7827 , Y10S257/90
摘要： A process is provided for forming a transistor in which the channel length is controlled by the depth of a trench etched into a semiconductor substrate. A masking layer extending across the substrate and a portion of the substrate are etched simultaneously to form the trench. A gate dielectric is formed upon the opposed sidewall surfaces of the trench. A pair of gate conductors are then formed upon the exposed lateral surfaces of the gate dielectric and the masking layer. Subsequently, an unmasked region of the substrate underneath the trench is implanted with dopant species and then annealed to form a source junction. The anneal temperature is preferably sufficient to cause the dopant species in the source junction to migrate laterally past the opposed sidewall surfaces of the trench. Drain junctions may subsequently be formed within the substrate a spaced distance above the source region on opposite sides of the trench. The physical channel length of the resulting transistors is thus defined as the distance between a source region and an overlying drain region. The channel of each transistor is spaced laterally from a gate conductor by a gate dielectric.
摘要翻译：提供了一种用于形成晶体管的工艺，其中沟道长度被蚀刻到半导体衬底中的沟槽的深度控制。同时蚀刻跨过衬底延伸的掩模层和衬底的一部分以形成沟槽。栅极电介质形成在沟槽的相对的侧壁表面上。然后在栅极电介质和掩蔽层的暴露的侧表面上形成一对栅极导体。随后，在沟槽下面的衬底的未掩蔽区域注入掺杂剂种类，然后退火以形成源极结。退火温度优选足以使源极结中的掺杂物质横向迁移通过沟槽的相对的侧壁表面。随后可以在衬底的相对侧上的源极区域上方间隔开距离处形成漏极结。因此，所得晶体管的物理沟道长度被定义为源极区域和上覆漏极区域之间的距离。每个晶体管的沟道通过栅极电介质与栅极导体横向隔开。

43. 发明授权

US06188114B1 Method of forming an insulated-gate field-effect transistor with metal spacers 有权
标题翻译：用金属间隔物形成绝缘栅场效应晶体管的方法
公开(公告)号：US06188114B1
公开(公告)日：2001-02-13
申请号：US09204016
申请日：1998-12-01
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L31119
CPC分类号： H01L29/41783 , H01L29/41775 , H01L29/66575 , H01L29/6659
摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.
摘要翻译：公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。金属间隔物还可以提供低电阻漏极和源极触点。

44. 发明授权

US06188107B1 High performance transistor fabricated on a dielectric film and method of making same 有权
标题翻译：在介电膜上制造的高性能晶体管及其制造方法
公开(公告)号：US06188107B1
公开(公告)日：2001-02-13
申请号：US09226564
申请日：1999-01-07
申请人： Mark I. Gardner , Frederick N. Hause , Derick J. Wristers
发明人： Mark I. Gardner , Frederick N. Hause , Derick J. Wristers
IPC分类号： H01L2900
CPC分类号： H01L29/78696 , H01L29/66757 , H01L29/78636
摘要： The present invention is directed to a transistor formed above a layer of a dielectric material and a method of making same. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a plurality of source/drain regions comprised of polysilicon above said layer of dielectric material and between said source/drain regions. The method further comprises forming a gate dielectric above said layer of polysilicon and forming a gate conductor above said gate dielectric. The transistor structure is comprised of a layer of dielectric material, a plurality of source/drain regions positioned above the layer of dielectric material, and a layer of polysilicon positioned above said layer of dielectric material and between said source/drain regions. The structure further comprises a gate dielectric positioned above said layer of polysilicon and a gate conductor positioned above said gate dielectric.
摘要翻译：本发明涉及一种形成在电介质材料层上方的晶体管及其制造方法。在一个说明性实施例中，所述方法包括形成介电材料层，在所述源极/漏极区之间形成由多晶硅上方的多个源极/漏极区域组成的电介质材料层。该方法还包括在所述多晶硅层上形成栅极电介质，并在所述栅极电介质上方形成栅极导体。晶体管结构由介电材料层，位于介电材料层之上的多个源极/漏极区域和位于介电材料层上方之间以及所述源极/漏极区域之间的多晶硅层构成。该结构还包括位于所述多晶硅层上方的栅极电介质和位于所述栅极电介质上方的栅极导体。

45. 发明授权

US06177687B1 Semiconductor device having gate electrode shared between two sets of active regions and fabrication thereof 有权
标题翻译：具有在两组有源区域之间共享的栅电极的半导体器件及其制造
公开(公告)号：US06177687B1
公开(公告)日：2001-01-23
申请号：US09201995
申请日：1998-12-01
申请人： Mark I. Gardner , H. Jim Fulford
发明人： Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L2916
CPC分类号： H01L27/0688 , H01L21/8221
摘要： Semiconductor devices having a gate electrode shared by two sets of active regions and methods of manufacture thereof are provided. In one embodiment, a first substrate is provided and a gate electrode is disposed over the first substrate. A second substrate is disposed over the gate electrode. A first set of active regions is disposed in portions of the first substrate adjacent the gate electrode and a second set of active regions is disposed above the gate electrode and adjacent the second substrate. The two sets of active regions may be coupled together or used separately.
摘要翻译：提供具有由两组活性区域共享的栅电极的半导体器件及其制造方法。在一个实施例中，提供第一基板并且在第一基板上设置栅电极。第二衬底设置在栅电极之上。第一组有源区设置在与栅电极相邻的第一衬底的部分中，并且第二组有源区设置在栅电极上方并与第二衬底相邻。两组有源区可以耦合在一起或单独使用。

46. 发明授权

US06172407B2 Source/drain and lightly doped drain formation at post interlevel dielectric isolation with high-K gate electrode design 失效
标题翻译：在高K栅电极设计的后级间隔介质隔离时的源/漏和轻掺杂漏极形成
公开(公告)号：US06172407B2
公开(公告)日：2001-01-09
申请号：US09061552
申请日：1998-04-16
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L2972
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28518 , H01L21/76801 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66575 , H01L29/6659
摘要： An integrated circuit fabrication process is provided in which a gate electrode including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, sidewall spacers are formed laterally adjacent opposed sidewall surfaces of the gate electrode. An interlevel dielectric is then formed above the semiconductor substrate and selectively removed from above active regions of the semiconductor substrate to form an opening. Source and drain implant areas are formed self-aligned with the opposed sidewall spacers. A metal silicide layer may be formed across upper surfaces of the gate conductor and source and drain areas, a second interlevel dielectric deposited in the opening, and contacts formed through the second interlevel dielectric to the metal silicide. In an alternative embodiment, the gate dielectric may be formed sufficiently thick such that sidewall spacers are unnecessary to prevent silicide bridging between the gate conductor and the junction regions. In another alternative embodiment, the lightly doped drain implant areas may be formed self-aligned to the gate electrode prior to spacer formation.
摘要翻译：提供一种集成电路制造工艺，其中在半导体衬底上形成包括栅极电介质和栅极导体的栅电极。优选地，栅极电介质的介电常数大于二氧化硅的介电常数。在一个实施例中，侧壁间隔件横向地形成在栅电极的相对侧壁表面上。然后在半导体衬底之上形成层间电介质，并从半导体衬底的上述有源区选择性地移除以形成开口。源极和漏极注入区域与相对的侧壁间隔物自对准地形成。可以在栅极导体和源极和漏极区域的上表面，沉积在开口中的第二层间电介质和通过第二层间电介质形成的触点与金属硅化物形成金属硅化物层。在替代实施例中，栅极电介质可以被形成为足够厚，使得不需要侧壁间隔物以防止栅极导体和接合区域之间的硅化物桥接。在另一替代实施例中，在间隔物形成之前，轻掺杂漏极注入区域可以形成为与栅电极自对准。

47. 发明授权

US06172381B2 Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall 有权
标题翻译：源极/漏极结区域在侧壁间隔物和蚀刻的侧壁之间自对准
公开(公告)号：US06172381B2
公开(公告)日：2001-01-09
申请号：US09219146
申请日：1998-12-22
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L2702
CPC分类号： H01L21/76897 , H01L21/76838 , H01L21/8221 , H01L23/5226 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer. The second transistor has a pair of implant regions spaced from each other by a gate conductor and a pair of oxide spacers arranged on opposed sidewall surfaces of the gate conductor. Part of the polysilicon layer is removed such that polysilicon only extends under the gate conductor and terminates a pre-defined distance from each of the pair of oxide spacers. A pair of junctions remain for the second transistor that are defined between an etched lateral edge and an oxide spacer. A second interlevel dielectric may be deposited across the second transistor and exposed areas of the primary interlevel dielectric to isolate the transistor from other active devices.
摘要翻译：提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构并将其与位于同一高架平面中的另一多晶硅结构隔离。升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。提供了第一晶体管，其设置在硅基衬底上并且位于硅基衬底内。在晶体管和衬底两端沉积初级层间电介质。然后可以将多晶硅沉积在初级层间电介质上并使用离子注入进行掺杂。可以在多晶硅层的一部分上形成第二晶体管。第二晶体管具有通过栅极导体和布置在栅极导体的相对的侧壁表面上的一对氧化物隔离物彼此隔开的一对注入区域。去除多晶硅层的一部分，使得多晶硅仅在栅极导体下方延伸并且终止与一对氧化物间隔物中的每一个的预定距离。在蚀刻的侧边缘和氧化物间隔物之间限定的第二晶体管保留一对结。可以跨越第二晶体管和初级层间电介质的暴露区域沉积第二层间电介质以将晶体管与其它有源器件隔离。

48. 发明授权

US06169306A Semiconductor devices comprised of one or more epitaxial layers 失效
标题翻译：由一个或多个外延层组成的半导体器件
公开(公告)号：US06169306A
公开(公告)日：2001-01-02
申请号：US09122833
申请日：1998-07-27
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L27108
CPC分类号： H01L29/517 , H01L21/28167 , H01L21/28194 , H01L27/105 , H01L27/11526 , H01L27/11543
摘要： The present invention is directed to a novel semiconductor device and a method for making same. As disclosed herein, a gate dielectric comprised of epitaxial metal oxide is positioned above a semiconducting substrate. A gate conductor comprised of an epitaxial conductive material is positioned above the gate dielectric. The method comprises forming a layer of an epitaxial metal oxide above a semiconducting substrate, forming a layer of epitaxial conductive material above the layer of epitaxial metal oxide, and forming a source/drain region.
摘要翻译：本发明涉及一种新颖的半导体器件及其制造方法。如本文所公开的，由外延金属氧化物组成的栅极电介质位于半导体衬底之上。由外延导电材料构成的栅极导体位于栅极电介质的上方。该方法包括在半导体衬底上形成外延金属氧化物层，在外延金属氧化物层之上形成外延导电材料层，形成源/漏区。

49. 发明授权

US6166354A System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication 失效
标题翻译：用于半导体制造中退火的原位监测和控制的系统和装置
公开(公告)号：US6166354A
公开(公告)日：2000-12-26
申请号：US876381
申请日：1997-06-16
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： C30B31/12 , C30B31/18 , F27B5/14
CPC分类号： C30B31/18 , C30B31/12
摘要： An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface of a substrate wafer to determine when the substrate is fully annealed. The surface photovoltage measurement is monitored, the time of annealing is detected, and a selected over-anneal is controlled. The surface photovoltage (SPV) measurement is performed to determine a point at which a dopant or impurity such as boron or phosphorus is annealed in a silicon lattice. In some embodiments, the point of detection is used as a feedback signal in an RTA annealing system to adjust a bank of annealing lamps for annealing and activation uniformity control. The point of detection is also used to terminate the annealing process to minimize D.sub.t.
摘要翻译：在退火步骤期间执行半导体器件的电特性的光学监测，以检测时间退火完成并发生激活。在退火期间进行表面光电压测量以监测衬底晶片的表面上的电荷状态，以确定衬底何时完全退火。监测表面光电压测量，检测退火时间，并控制所选择的过退火。执行表面光电压（SPV）测量以确定在硅晶格中退火掺杂剂或杂质如硼或磷的点。在一些实施例中，将检测点用作RTA退火系统中的反馈信号，以调整用于退火和激活均匀性控制的退火灯组。检测点也用于终止退火过程以最小化Dt。

50. 发明授权

US6163060A Semiconductor device with a composite gate dielectric layer and gate barrier layer and method of making same 有权
标题翻译：具有复合栅极介电层和栅极阻挡层的半导体器件及其制造方法
公开(公告)号：US6163060A
公开(公告)日：2000-12-19
申请号：US163673
申请日：1998-09-30
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L21/28 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention is directed to a new semiconductor device and a method for making same. The new semiconductor device is comprised of a gate barrier layer, a composite gate dielectric layer, a conductor layer, and at least one source/drain region formed in aemiconducting substrate. The method comprises forming the gate barrier layer, composite gate dielectric layer and conductor layer, patterning those layers, and forming at least one source/drain region in said semiconductor substrate. The composite gate dielectric layer is comprised of at least two different materials having different dielectric constants.
摘要翻译：本发明涉及一种新的半导体器件及其制造方法。新的半导体器件由栅极阻挡层，复合栅极电介质层，导体层和形成在半导体衬底中的至少一个源极/漏极区域组成。该方法包括形成栅极阻挡层，复合栅极电介质层和导体层，图案化这些层，并在所述半导体衬底中形成至少一个源极/漏极区域。复合栅极电介质层由具有不同介电常数的至少两种不同材料组成。

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