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41. 发明授权

US07262107B2 Capacitor structure for a logic process 有权
公开(公告)号：US07262107B2
公开(公告)日：2007-08-28
申请号：US11170504
申请日：2005-06-29
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： H01L21/331
CPC分类号： H01L27/108 , H01L27/1085 , H01L28/40
摘要： A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.

42. 发明授权

US07236410B2 Memory cell driver circuits 有权
标题翻译：存储单元驱动电路
公开(公告)号：US07236410B2
公开(公告)日：2007-06-26
申请号：US11169106
申请日：2005-06-27
申请人： Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Dinesh Somasekhar , Yibin Ye , Ali Keshavarzi , Muhammad M. Khellah , Vivek K. De
发明人： Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Dinesh Somasekhar , Yibin Ye , Ali Keshavarzi , Muhammad M. Khellah , Vivek K. De
IPC分类号： G11C7/00 , G11C17/00 , G11C5/06
CPC分类号： G11C17/18
摘要： A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
摘要翻译：系统包括用于对存储器单元进行编程的上拉电路。上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍，并产生第二控制信号和共源共栅级。共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道电压和输出节点以提供单元编程信号。

43. 发明授权

US07075821B2 Apparatus and method for a one-phase write to a one-transistor memory cell array 失效
公开(公告)号：US07075821B2
公开(公告)日：2006-07-11
申请号：US10956407
申请日：2004-09-30
申请人： Yibin Ye , Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Gerhard Schrom , Vivek K. De
发明人： Yibin Ye , Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Gerhard Schrom , Vivek K. De
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C2211/4016
摘要： A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.

44. 发明授权

US07057927B2 Floating-body dynamic random access memory with purge line 失效
标题翻译：具有清除线的浮动动态随机存取存储器
公开(公告)号：US07057927B2
公开(公告)日：2006-06-06
申请号：US11289621
申请日：2005-11-30
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien Lu , Vivek K. De
IPC分类号： G11C11/34
CPC分类号： H01L27/108 , G11C11/404
摘要： Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.
摘要翻译：实施例涉及浮体动态随机存取存储器（FBDRAM）。在将数据写入FBDRAM单元之前，FBDRAM利用清除线来复位FBDRAM单元。

45. 发明授权

US06952376B2 Method and apparatus to generate a reference value in a memory array 有权
公开(公告)号：US06952376B2
公开(公告)日：2005-10-04
申请号：US10740551
申请日：2003-12-22
申请人： Dinesh Somasekhar , Yibin Ye , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek K. De
IPC分类号： G11C7/14 , G11C7/18 , G11C11/4097 , G11C11/4099 , G11C7/02
CPC分类号： G11C11/4099 , G11C7/14 , G11C7/18 , G11C11/4097
摘要： An apparatus and method for generating a reference in a memory circuit are disclosed. At least two dummy bit-cells are used to generate a reference voltage. One cell has high value stored and the other has a low value stored. The cells are activated and discharged into respective bit-lines. The bit-lines are equalized during the discharge process to generate a reference that is approximately a mid point between a high value cell and a low value cell.

46. 发明授权

US06909652B2 SRAM bit-line reduction 失效
标题翻译： SRAM位线减少
公开(公告)号：US06909652B2
公开(公告)日：2005-06-21
申请号：US10305753
申请日：2002-11-26
申请人： Yibin Ye , Dinesh Somasekhar , Muhammad M. Khellah , Vivek K. De
发明人： Yibin Ye , Dinesh Somasekhar , Muhammad M. Khellah , Vivek K. De
IPC分类号： G11C7/12 , G11C11/412 , G11C7/00
CPC分类号： G11C7/12 , G11C11/412
摘要： A SRAM with reduced subthreshold leakage current, the SRAM including a pMOSFET with its gate at VSS and its source at VCC, and a diode-connected pMOSFET with its source at VCC, where the drains of the pMOSFET and the diode-connected pMOSFET are connected together to provide a voltage VCCL, where VSS
摘要翻译：具有降低的亚阈值漏电流的SRAM，SRAM包括其栅极为V SS的pMOSFET及其源极为V CC，以及二极管连接的pMOSFET，其源极为其中pMOSFET和二极管连接的pMOSFET的漏极连接在一起，以提供一个电压V CCL，其中V SS SS < CCL CC 。二极管连接的pMOSFET的β基本上大于pMOSFET的β。在读取操作期间，与每个存储器单元相关联的字线被驱动到电压-V EE EE，其中-V SS和/ CCL <=> CC CCL 。每个存储单元具有交叉耦合的反相器以存储数据位，其中交叉耦合的反相器具有其源极为V CCL 的pMOSFET。

47. 发明授权

US06876571B1 Static random access memory having leakage reduction circuit 有权
标题翻译：具有泄漏降低电路的静态随机存取存储器
公开(公告)号：US06876571B1
公开(公告)日：2005-04-05
申请号：US10738220
申请日：2003-12-18
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De
IPC分类号： G11C11/00 , G11C11/412
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) is provided that includes a logic circuit coupled to a column select signal line and a leakage reduction circuit coupled to the logic circuit and a bit line pair of a column. The logic circuit may control the leakage reduction circuit so as to reduce leakage through a column select device that is not selected.
摘要翻译：提供了一种静态随机存取存储器（SRAM），其包括耦合到列选择信号线的逻辑电路和耦合到逻辑电路和列的位线对的泄漏减少电路。逻辑电路可以控制泄漏减少电路，以便减少未被选择的列选择装置的泄漏。

48. 发明授权

US07120804B2 Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency 有权
标题翻译：用于通过动态控制电源电压和身体偏压来降低功耗的方法和装置，包括保持基本恒定的工作频率
公开(公告)号：US07120804B2
公开(公告)日：2006-10-10
申请号：US10328573
申请日：2002-12-23
申请人： James W. Tschanz , Yibin Ye , Liqiong Wei , Vivek K. De
发明人： James W. Tschanz , Yibin Ye , Liqiong Wei , Vivek K. De
IPC分类号： G06F1/26 , H03K3/01
CPC分类号： G06F1/3296 , G06F1/3203 , H03K2217/0018 , Y02D10/126 , Y02D10/172
摘要： An approach for power reduction of an integrated circuit device. In response to detecting a change in an activity factor associated with an integrated circuit device from a first activity factor to a second activity factor, a supply voltage and a body bias associated with the integrated circuit device are adjusted based on the second activity factor to reduce power consumption. For one aspect, the supply voltage and body bias are adjusted to maintain a substantially constant operating frequency for the integrated circuit device.
摘要翻译：一种用于集成电路装置的功率降低的方法。响应于检测到与集成电路器件相关联的活动因素从第一活动因素到第二活动因素的变化，基于第二活动因素来调整与集成电路设备相关联的电源电压和身体偏差以减少能量消耗。一方面，调整电源电压和体偏置以保持集成电路器件的基本恒定的工作频率。

49. 发明授权

US06744301B1 System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise 有权
标题翻译：系统使用身体偏置的睡眠晶体管来减少泄漏功率，同时最大限度地降低性能损失和噪音
公开(公告)号：US06744301B1
公开(公告)日：2004-06-01
申请号：US09707528
申请日：2000-11-07
申请人： James W. Tschanz , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G05F302
CPC分类号： G05F3/205
摘要： A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.
摘要翻译：公开了一种降低泄漏功率同时最小化性能损失和噪声的系统和方法。根据本发明的一个实施例，该系统包括至少一个休眠晶体管，其可操作地耦合在系统电源和由系统电源供电的至少一个电路之间，以控制对电路的功率的施加。休眠晶体管也可操作地耦合以接收睡眠控制信号以打开和关闭睡眠晶体管。身体偏置电压发生器可操作地耦合到至少一个睡眠晶体管的主体，以在休眠晶体管不可操作或空闲时基本上减少泄漏电流，并且当晶体管通过降低工作时改善睡眠晶体管的操作特性休眠晶体管的性能损失，并减少噪声对电路和其他器件的影响。

50. 发明授权

US06515513B2 Reducing leakage currents in integrated circuits 有权
公开(公告)号：US06515513B2
公开(公告)日：2003-02-04
申请号：US09846604
申请日：2001-04-30
申请人： Yibin Ye , James W. Tschanz , Vivek K. De
发明人： Yibin Ye , James W. Tschanz , Vivek K. De
IPC分类号： H03K190175
CPC分类号： H03K19/0016
摘要： A method and apparatus for reducing leakage current in an integrated circuit includes a supply voltage line, a virtual supply voltage line, a ground voltage line, a virtual ground voltage line, a first logic circuit coupled to the ground voltage line and selectively coupled to the virtual supply voltage line, a second logic circuit coupled to the supply voltage line and selectively coupled to the virtual ground voltage line, and a switch circuit configured to control the selective coupling of the first logic circuit to the virtual supply line voltage and the second logic circuit to the virtual ground voltage line.

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