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    • 41. 发明申请
    • Method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a top cladding
    • 通过选择顶部包层的波导芯宽度来控制波导双折射的方法和装置
    • US20080240655A1
    • 2008-10-02
    • US12079930
    • 2008-03-28
    • Farnaz ParhamiLiang ZhaoFan Zhong
    • Farnaz ParhamiLiang ZhaoFan Zhong
    • G02B6/34G02B6/10
    • G02B6/12023G02B6/126
    • A method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a tuned top clad is described herein. In one example, a dopant concentration within a top cladding material is between 3-6% (wt.). Given a tuned top cladding composition, a width of the waveguide core is pre-selected such that birefringence is minimized, i.e., a zero, or near zero. The desirable width of the waveguide core is determined by calculating the distribution of stress in the top cladding over a change in temperature. From this distribution of stress, a relationship between the polarization dependent wavelength and variable widths of the waveguide in the arrayed waveguide grating are determined. This relationship determines a zero value, or near zero value, of polarization dependent wavelength for a given range of waveguide widths. Accordingly, the width of the waveguide may be selected such that the polarization dependent wavelength is minimized.
    • 本文描述了通过选择用于调谐顶部包层的波导芯宽度来控制波导双折射的方法和装置。 在一个实例中,顶部包层材料内的掺杂剂浓度在3-6%(重量)之间。 给定一个调整的顶部包层组成,预先选择波导芯的宽度,使得双折射最小化,即零或接近零。 通过计算在顶部包层中的应力在温度变化中的分布来确定波导芯的期望宽度。 根据这种应力分布,确定阵列波导光栅中波导的偏振相关波长与可变宽度之间的关系。 对于给定的波导宽度范围,该关系确定偏振相关波长的零值或近零值。 因此,可以选择波导的宽度使得偏振相关波长最小化。
    • 42. 发明授权
    • GeBPSG top clad for a planar lightwave circuit
    • GeBPSG顶部包层用于平面光波电路
    • US07372121B2
    • 2008-05-13
    • US11591085
    • 2006-11-01
    • Fan ZhongMichael Lennon
    • Fan ZhongMichael Lennon
    • H01L31/0232G02B6/10
    • C23C16/401G02B6/122G02B2006/121
    • A method of depositing a top clad layer for an optical waveguide of a planar lightwave circuit. A GeBPSG top clad layer for an optical waveguide structure of a planar lightwave circuit is fabricated such that the top clad layer comprises doped silica glass, wherein the dopant includes Ge (Germanium), P (Phosphorus), and B (Boron). In depositing a top clad layer for the optical waveguide, three separate doping gasses (e.g., GeH4, PH3, and B2H6) are added during the PECVD (plasma enhanced chemical vapor deposition) process to make Ge, P and B doped silica glass (GeBPSG). The ratio of the Ge, P, and B dopants is configured to reduce the formation of crystallization areas within the top clad layer and maintain a constant refractive index within the top clad layer across an anneal temperature range. A thermal anneal process for the top clad layer can be a temperature within a range of 950 C to 1050 C. The GeBPSG top clad layer reduces the insertion loss of passive arrayed waveguide grating devices and active planar lightwave circuit devices.
    • 一种沉积用于平面光波电路的光波导的顶包层的方法。 制造用于平面光波电路的光波导结构的GeBPSG顶包层,使得顶覆层包括掺杂的石英玻璃,其中掺杂剂包括Ge(锗),P(磷)和B(硼)。 在沉积用于光波导的顶部包覆层时,三个单独的掺杂气体(例如,GeH 4,PH 3 3和B 2 H) 在PECVD(等离子体增强化学气相沉积)工艺中添加制备Ge,P和B掺杂的石英玻璃(GeBPSG)的工艺。 Ge,P和B掺杂剂的比例被配置为减少顶部包层内的结晶区域的形成,并且在整个退火温度范围内在顶部包覆层内保持恒定的折射率。 用于顶部包层的热退火工艺可以是在950℃至1050℃范围内的温度.GeBPSG顶部包层降低了无源阵列波导光栅器件和有源平面光波电路器件的插入损耗。
    • 43. 发明授权
    • GePSG core for a planar lightwave circuit
    • GePSG内核,用于平面光波电路
    • US06615615B2
    • 2003-09-09
    • US09895583
    • 2001-06-29
    • Fan ZhongJonathan G. Bornstein
    • Fan ZhongJonathan G. Bornstein
    • G02B610
    • G02B6/12023G02B6/105G02B6/122G02B6/132G02B2006/12169
    • A method of depositing a core layer for an optical waveguide structure of a planar lightwave circuit. A GePSG core for an optical waveguide structure of a planar lightwave circuit is fabricated such that the optical core comprises doped silica glass, wherein the dopant includes Ge and P. In depositing a core layer from which the optical core is formed, two separate doping gasses (e.g., GeH4 and PH3) are added during the PECVD process to make Ge and P doped silica glass (GePSG). The ratio of the Ge dopant and the P dopant is configured to maintain a constant refractive index within the core layer across an anneal temperature range and to reduce a formation of bubbles within the core layer. The ratio of the Ge dopant and the P dopant is also configured to reduce refractive index birefringence within the core layer across an anneal temperature range.
    • 一种沉积用于平面光波电路的光波导结构的芯层的方法。 制造用于平面光波电路的光波导结构的GePSG芯,使得光芯包括掺杂的石英玻璃,其中掺杂剂包括Ge和P.在沉积形成有光纤芯的芯层时,两个单独的掺杂气体 (例如,GeH 4和PH 3)在PECVD工艺中被添加以制造Ge和P掺杂的石英玻璃(GePSG)。 Ge掺杂剂和P掺杂剂的比例被配置为在整个退火温度范围内在芯层内保持恒定的折射率,并且减小芯层内的气泡的形成。 Ge掺杂剂和P掺杂剂的比例还被配置为在整个退火温度范围内降低芯层内的折射率双折射。
    • 45. 发明申请
    • PIXEL VIA AND METHODS OF FORMING THE SAME
    • 像素及其形成方法
    • US20120248478A1
    • 2012-10-04
    • US13079487
    • 2011-04-04
    • Hojin LeeFan ZhongYi Tao
    • Hojin LeeFan ZhongYi Tao
    • H01L33/44H01L33/60
    • G02B26/001
    • This disclosure provides systems, methods and apparatuses for pixel vias. In one aspect, a method of forming an electromechanical device having a plurality of pixels includes depositing an electrically conductive black mask on a substrate at each of four corners of each pixel, depositing a dielectric layer over the black mask, depositing an optical stack including a stationary electrode over the dielectric layer, depositing a mechanical layer over the optical stack, and anchoring the mechanical layer over the optical stack at each corner of each pixel. The method further includes providing a conductive via in a first pixel of the plurality of pixels, the via in the dielectric layer electrically connecting the stationary electrode to the black mask, the via disposed at a corner of the first pixel, offset from where the mechanical layer is anchored over the optical stack in an optically non-active area of the first pixel.
    • 本公开提供了用于像素通孔的系统,方法和装置。 一方面,一种形成具有多个像素的机电装置的方法包括:在每个像素的四个角中的每一个的基板上沉积导电黑色掩模,在黑色掩模上沉积介电层,沉积包括 在电介质层上沉积固定电极,在光学堆叠上沉积机械层,并将机械层固定在每个像素的每个角落的光学堆叠上。 所述方法还包括在所述多个像素的第一像素中提供导电通孔,所述电介质层中的所述通孔将所述固定电极电连接到所述黑色掩模,所述通孔设置在所述第一像素的拐角处,偏离所述机械 层在第一像素的光学非有效区域中锚定在光学堆叠上。
    • 47. 发明申请
    • MECHANICAL LAYER AND METHODS OF FORMING THE SAME
    • 机械层及其形成方法
    • US20110249315A1
    • 2011-10-13
    • US13082955
    • 2011-04-08
    • Yi TaoFan Zhong
    • Yi TaoFan Zhong
    • G02B26/00B32B38/10B32B37/02
    • G02B26/001
    • This disclosure provides mechanical layers and methods of forming the same. In one aspect, an electromechanical systems device includes a substrate and a mechanical layer having an actuated position and a relaxed position. The mechanical layer is spaced from the substrate to define a collapsible gap. The gap is in a collapsed condition when the mechanical layer is in the actuated position and in a non-collapsed condition when the mechanical layer is in the relaxed position. The mechanical layer includes a reflective layer, a conductive layer, and a supporting layer. The supporting layer is positioned between the reflective layer and the conductive layer and is configured to support the mechanical layer.
    • 本公开提供了机械层及其形成方法。 一方面,机电系统装置包括基板和具有致动位置和松弛位置的机械层。 机械层与衬底间隔开以限定可折叠间隙。 当机械层处于松弛位置时,机械层处于致动位置并处于非塌陷状态时,间隙处于折叠状态。 机械层包括反射层,导电层和支撑层。 支撑层位于反射层和导电层之间,并被构造成支撑机械层。
    • 48. 发明申请
    • DISPLAY DEVICE WITH OPENINGS BETWEEN SUB-PIXELS AND METHOD OF MAKING SAME
    • 具有子像素之间的开口的显示装置及其制造方法
    • US20100238572A1
    • 2010-09-23
    • US12409425
    • 2009-03-23
    • Yi TaoFan Zhong
    • Yi TaoFan Zhong
    • G02B7/182H01L21/00
    • G02B26/001B81B3/0086B81B2201/047B81B2203/053B81B2207/053
    • An electromechanical systems device includes a plurality of supports disposed over a substrate and a deformable reflective layer disposed over the plurality of supports. The deformable reflective layer includes a plurality of substantially parallel columns extending in a first direction. Each column has one or more slots extending in a second direction generally perpendicular to the first direction. The slots can be created at boundary edges of sub-portions of the columns so as to partially mechanically separate the sub-portions without electrically disconnecting them. A method of fabricating an electromechanical device includes depositing an electrically conductive deformable reflective layer over a substrate, removing one or more portions of the deformable layer to form a plurality of electrically isolated columns, and forming at least one crosswise slot in at least one of the columns.
    • 机电系统装置包括设置在基板上的多个支撑件和设置在多个支撑件上的可变形反射层。 可变形反射层包括沿第一方向延伸的多个大致平行的列。 每列具有一个或多个槽,其大致垂直于第一方向在第二方向上延伸。 可以在列的子部分的边界边缘处创建槽,以便部分地机械地分离子部分而不断开它们。 制造机电装置的方法包括在衬底上沉积导电的可变形反射层,去除可变形层的一个或多个部分以形成多个电隔离的柱,并且在至少一个 列。
    • 50. 发明授权
    • Top cap process for reducing polarization dependent wavelength shift in planar lightwave circuits
    • 用于减小平面光波电路中的偏振相关波长偏移的顶盖工艺
    • US06826345B1
    • 2004-11-30
    • US10165903
    • 2002-06-10
    • Fan ZhongFarnaz ParhamiZhigang Zhou
    • Fan ZhongFarnaz ParhamiZhigang Zhou
    • G02B610
    • G02B6/126G02B2006/121
    • One aspect of the invention relates to a PLC containing at least one waveguide on a bottom clad layer, each waveguide having a top cap layer on an upper surface thereof, and a top clad layer over the waveguides having the top cap on the upper portion thereof. The presence of the top cap reduces waveguide birefringence and resultant polarization dependence in PLCs, particularly for reducing polarization dependent wavelength shift in AWGs. Another aspect of the invention relates to methods of making PLCs involving forming a waveguide layer on a bottom clad layer, forming a top cap layer on the waveguide layer, patterning the waveguide layer and the top cap layer using a mask to form waveguides having a top cap on an upper portion thereof, and forming a top clad layer over the waveguides having the top cap on the upper portion thereof.
    • 本发明的一个方面涉及一种在底部包层上含有至少一个波导的PLC,每个波导在其上表面上具有顶盖层,并且在该波导上方的顶部覆盖层在其上部具有顶盖 。 顶盖的存在降低了PLC中的波导双折射和合成极化依赖性,特别是为了减少AWG中的偏振相关波长偏移。 本发明的另一方面涉及制造PLC的方法,其涉及在底部包层上形成波导层,在波导层上形成顶盖层,使用掩模对波导层和顶盖层进行图案化以形成具有顶部的波导 盖在其上部,并且在其上部具有顶盖的波导上形成顶部包层。