专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07029980B2 Method of manufacturing SOI template layer 有权
标题翻译：制造SOI模板层的方法
公开(公告)号：US07029980B2
公开(公告)日：2006-04-18
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/331
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

42. 发明申请

US20060040433A1 Graded semiconductor layer 有权
标题翻译：分级半导体层
公开(公告)号：US20060040433A1
公开(公告)日：2006-02-23
申请号：US10919952
申请日：2004-08-17
申请人： Mariam Sadaka , Shawn Thomas , Ted White , Chun-Li Liu , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam Sadaka , Shawn Thomas , Ted White , Chun-Li Liu , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/84
CPC分类号： H01L29/78687 , H01L29/1054 , H01L29/6659 , H01L29/66742
摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
摘要翻译：一种形成半导体器件的方法。该方法包括形成用于形成应变硅层的模板层。在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

43. 发明申请

US20050070057A1 Semiconductor layer formation 失效
标题翻译：半导体层形成
公开(公告)号：US20050070057A1
公开(公告)日：2005-03-31
申请号：US10919784
申请日：2004-08-17
申请人： Chun-Li Liu , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White , Qianghua Xie
发明人： Chun-Li Liu , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White , Qianghua Xie
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在加热晶片的同时使含氯气体（例如氯化氢，氯气，四氯化碳和三氯乙烷）流过晶片。在一个实例中，在用作形成应变半导体层（例如应变硅）的模板层的半导体层上的冷凝过程中，含有轴承气体流动。在其他实例中，在冷凝操作之后，在晶片的后烘烤期间，含氯气体流动。

44. 发明申请

US20050070053A1 Template layer formation 有权
标题翻译：模板层形成
公开(公告)号：US20050070053A1
公开(公告)日：2005-03-31
申请号：US10919922
申请日：2004-08-17
申请人： Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted White
发明人： Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted White
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming a strained semiconductor layer. The process includes implanting ions into a semiconductor layer prior to performing a condensation process on the layer. The ions assist in diffusion of atoms (e.g. germanium) in the semiconductor layer and to increase the relaxation of the semiconductor layer. After the condensation process, the layer can be used as a template layer for forming a strained semiconductor layer.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在层之前进行冷凝过程之前将离子注入到半导体层中。离子有助于半导体层中的原子（例如锗）的扩散并增加半导体层的松弛。在冷凝过程之后，该层可用作形成应变半导体层的模板层。

45. 发明申请

US20110227136A1 SPACER PROTECTION AND ELECTRICAL CONNECTION FOR ARRAY DEVICE 失效
标题翻译：阵列保护和电气连接
公开(公告)号：US20110227136A1
公开(公告)日：2011-09-22
申请号：US12728488
申请日：2010-03-22
申请人： Jae-Eun Park , Weipeng Li , Deleep R. Nair , M. Dean Sciacca , Voon-Yew Thean , Ava Wan , Dong-Hun Lee , Yong-Meng Lee
发明人： Jae-Eun Park , Weipeng Li , Deleep R. Nair , M. Dean Sciacca , Voon-Yew Thean , Ava Wan , Dong-Hun Lee , Yong-Meng Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/76895 , H01L29/665 , H01L29/6659
摘要： The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.
摘要翻译：本公开提供了形成电气装置的方法。该方法可以从衬底上形成栅极结构开始，其中间隔物直接与栅极结构的侧壁接触。源极区和漏极区形成在衬底中。在栅极结构上形成金属半导体合金，间隔物的外侧壁和源极区域和漏极区域中的一个。在金属半导体合金上形成层间电介质层。通过金属半导体合金上的层间电介质停止形成通孔。在通孔中的金属半导体合金形成互连。本公开还包括通过上述方法制造的结构。

46. 发明授权

US07867839B2 Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors 有权
标题翻译：降低硅锗（SiGe），高k电介质金属栅极，p型金属氧化物半导体场效应晶体管中的阈值电压（Vt）的方法
公开(公告)号：US07867839B2
公开(公告)日：2011-01-11
申请号：US12176634
申请日：2008-07-21
申请人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
发明人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/2652 , H01L21/823807 , H01L29/1054
摘要： Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
摘要翻译：公开了具有最佳阈值电压（Vt）的p型硅锗（SiGe），高k电介质金属栅极，金属氧化物半导体场效应晶体管（PFET），互补金属氧化物半导体（CMOS）器件其包括PFET和形成PFET单独和CMOS器件的方法。实施例将带负电荷的离子（例如，氟（F），氯（Cl），溴（Br），碘（I）等）并入PFET的高k栅介质材料中，以便选择性地调节 PFET的负Vt（即，以减小PFET的负Vt）。

47. 发明授权

US07811382B2 Method for forming a semiconductor structure having a strained silicon layer 有权
标题翻译：用于形成具有应变硅层的半导体结构的方法
公开(公告)号：US07811382B2
公开(公告)日：2010-10-12
申请号：US11421009
申请日：2006-05-30
申请人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
IPC分类号： C30B21/02
CPC分类号： C30B29/52 , C30B25/02 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/76254
摘要： A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, is thus also correlated to the germanium concentration of the relaxed SiGe layer. The thickness of the low temperature silicon layer, using the trisilane at low temperature, is significantly greater than what would normally be expected for a silicon layer of that tensile strain.
摘要翻译：具有应变的硅层的晶片用于形成晶体管。通过首先在施主晶片上形成具有松弛应变的至少30％的锗的锗锗（SiGe）层来形成硅层。外延生长薄硅层以在松弛的SiGe层上具有拉伸应变。拉伸应变量与锗浓度有关。优选在800至850摄氏度之间的温度下，通过使二氯硅烷和一氧化二氮反应，在薄硅层上形成高温氧化物（HTO）层。手柄晶片设置有支撑基板和氧化物层，然后将其结合到HTO层。高密度的HTO层能够保持薄硅层的拉伸应变。松弛的SiGe层被切割，然后蚀刻掉以露出薄的硅层。然后在优选不超过500摄氏度的温度下使用丙硅烷在薄硅层上外延生长与低硅薄层的拉伸应变相关的低温硅层。因此，与薄硅层的应变相关的所得拉伸应变也与弛豫SiGe层的锗浓度相关。在低温下使用丙硅烷的低温硅层的厚度明显大于该拉伸应变的硅层通常预期的厚度。

48. 发明授权

US07737496B2 Electronic devices including a semiconductor layer 有权
公开(公告)号：US07737496B2
公开(公告)日：2010-06-15
申请号：US11836844
申请日：2007-08-10
申请人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
发明人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
IPC分类号： H01L21/84
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

49. 发明申请

US20100027355A1 PLANAR DOUBLE GATE TRANSISTOR STORAGE CELL 审中-公开
标题翻译：平面双门晶体管存储单元
公开(公告)号：US20100027355A1
公开(公告)日：2010-02-04
申请号：US11831801
申请日：2007-07-31
申请人： Thuy B. Dao , Voon-Yew Thean , Bruce E. White
发明人： Thuy B. Dao , Voon-Yew Thean , Bruce E. White
IPC分类号： G11C7/00 , H01L29/78 , H01L21/336
CPC分类号： H01L29/66833 , B82Y10/00 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A semiconductor device suitable for use as a storage cell includes a semiconductor body having a top surface and a bottom surface, a top gate dielectric overlying the semiconductor body top surface, an electrically conductive top gate electrode overlying the top gate dielectric, a bottom gate dielectric underlying the semiconductor body bottom surface, an electrically conductive bottom gate electrode underlying the bottom gate dielectric, and a charge trapping layer. The charge trapping layer includes a plurality of shallow charge traps, adjacent the top or bottom surface of the semiconductor body. The charge trapping layer may be of aluminum oxide, silicon nitride, or silicon nanoclusters. The charge trapping layer may located positioned between the bottom gate dielectric and the bottom surface of the semiconductor body.
摘要翻译：适合用作存储单元的半导体器件包括具有顶表面和底表面的半导体本体，覆盖半导体本体顶表面的顶栅电介质，覆盖顶栅电介质的导电顶栅电极，底栅电介质在半导体本体底表面下方，位于底栅电介质底部的导电底栅电极和电荷捕获层。电荷捕获层包括与半导体本体的顶表面或底表面相邻的多个浅电荷陷阱。电荷捕获层可以是氧化铝，氮化硅或硅纳米团簇。电荷捕获层可以位于底栅电介质和半导体本体的底表面之间。

50. 发明申请

US20090291540A1 CMOS Process with Optimized PMOS and NMOS Transistor Devices 有权
标题翻译： CMOS工艺与优化的PMOS和NMOS晶体管器件
公开(公告)号：US20090291540A1
公开(公告)日：2009-11-26
申请号：US12125855
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34）以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式