专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08023325B2 Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
公开(公告)号：US08023325B2
公开(公告)日：2011-09-20
申请号：US13019048
申请日：2011-02-01
申请人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

42. 发明申请

US20080055986A1 SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS 失效
标题翻译：具有故障细胞的半导体存储器件
公开(公告)号：US20080055986A1
公开(公告)日：2008-03-06
申请号：US11931881
申请日：2007-10-31
申请人： Kunihiro KATAYAMA , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro KATAYAMA , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C29/24
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

43. 发明授权

US07234087B2 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：US07234087B2
公开(公告)日：2007-06-19
申请号：US10748156
申请日：2003-12-31
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00 , G11C11/34
CPC分类号： G06F11/1008
摘要： High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes sector data in one of the first memory and second memory, and next sector data in the other of the first and second memory. Sector data is read out from one of the first memory and second memory to the host computer, and simultaneously, next sector data is read out from the other of the first memory and second memory, and error detection and correction performed in the error correcting means. During a next cycle, the sector data read out from one of the first memory and second memory is outputted to the host computer, and simultaneously, error detection and error correction of the next sector data read out from one of the first computer and second computer is performed in the error correcting means.
摘要翻译：获得高速存储器访问和使用单个纠错装置的透明错误检测和校正。主计算机将扇区数据写入第一存储器和第二存储器之一，以及第一和第二存储器中的另一个中的下一扇区数据。扇区数据从第一存储器和第二存储器之一读出到主计算机，并且同时从第一存储器和第二存储器中的另一个读出下一个扇区数据，并且在纠错装置中执行错误检测和校正。在下一周期中，将从第一存储器和第二存储器之一读出的扇区数据输出到主计算机，同时，从第一计算机和第二计算机之一读出的下一个扇区数据的错误检测和纠错在纠错装置中执行。

44. 发明申请

US20070101047A1 Memory apparatus and controller 审中-公开
标题翻译：内存设备和控制器
公开(公告)号：US20070101047A1
公开(公告)日：2007-05-03
申请号：US10561795
申请日：2004-12-22
申请人： Kiyoshi Kamiya , Takayuki Tamura , Fumio Hara , Kunihiro Katayama
发明人： Kiyoshi Kamiya , Takayuki Tamura , Fumio Hara , Kunihiro Katayama
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C16/349 , G06F12/0246 , G11C16/3427
摘要： A memory apparatus having a rewritable nonvolatile memory, and a control circuit. The memory apparatus brings logical addresses into correspondence with physical addresses of the nonvolatile memory and retains a piece of number-of-rewrites information for each logical address. The control circuit can perform a replacement process of a piece of memory information on the nonvolatile memory. In the replacement process, a given logical address judged to have a small number of rewrites based on the number-of-rewrites information is replaced so as to correspond to a different physical address and then data is transferred according to the replacement. Even when data of the logical address smaller in the number of rewrites is assigned to the different physical address, the number of rewrites of the region is still grasped as the number of rewrites of the logical address. The data of the logical address is maintained in a condition such that it can be easily targeted for the rewrite by the replacement process even in the place to which the data is transferred. Thus, a memory cell is made less prone to accumulatively suffering disturb owing to rewrite.
摘要翻译：具有可重写非易失性存储器的存储装置和控制电路。存储装置使逻辑地址与非易失性存储器的物理地址相对应，并且为每个逻辑地址保留一段重写数量的信息。控制电路可以在非易失性存储器上执行一条存储器信息的替换处理。在替换处理中，基于重写信息信息判断为具有少量重写的给定逻辑地址被替换为对应于不同的物理地址，然后根据替换来传送数据。即使将重写次数较小的逻辑地址的数据分配给不同的物理地址，也可以将该区域的重写次数作为逻辑地址的重写次数来掌握。逻辑地址的数据被保持在这样的状态，使得即使在数据被传送到的地方也可以容易地通过替换处理进行重写。因此，由于重写，存储器单元不容易累积地受到干扰。

45. 发明申请

US20060062045A1 Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
公开(公告)号：US20060062045A1
公开(公告)日：2006-03-23
申请号：US11206995
申请日：2005-08-19
申请人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

46. 发明授权

US06701471B2 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：US06701471B2
公开(公告)日：2004-03-02
申请号：US09750707
申请日：2001-01-02
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C2900
CPC分类号： G06F11/1008
摘要： High-speed memory access and transparent error detection and correction using a single error correcting means are obtained and processed by an external storage device of a host computer when sector data having an arbitrary byte width are accessed continuously according to a size of a sector unit. Consequently, the host computer always reads sector data, and at the same time, error detection and the error correction for a next sector data are simultaneously performed, thereby greatly reducing the time required for error detection and error correction, and high speed memory access can be obtained.
摘要翻译：当根据扇区单元的大小连续访问具有任意字节宽度的扇区数据时，由主计算机的外部存储设备获得并处理高速存储器访问和使用单个纠错装置的透明错误检测和校正。因此，主计算机总是读取扇区数据，同时执行错误检测和下一个扇区数据的纠错，从而大大减少了错误检测和纠错所需的时间，高速存储器存取可以得到。

47. 发明授权

US06683812B2 Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
公开(公告)号：US06683812B2
公开(公告)日：2004-01-27
申请号：US10304046
申请日：2002-11-26
申请人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C700
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell. As a result of these operations, the semiconductor memory can determine the pieces of bit data in the order of the buffer A and the buffer B every time the discriminating operation is performed with respect to the cell.

48. 发明授权

US06388920B2 Semiconductor memory device having faulty cells 有权
公开(公告)号：US06388920B2
公开(公告)日：2002-05-14
申请号：US09886133
申请日：2001-06-22
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C1606
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

49. 发明授权

US06317371B2 Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory 有权
标题翻译：具有错误校正单元的存储设备和用于访问和传送存储在非易失性半导体存储器中的数据块的改进布置
公开(公告)号：US06317371B2
公开(公告)日：2001-11-13
申请号：US09824778
申请日：2001-04-04
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C700
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

50. 发明授权

US06236601B1 Semiconductor memory device having faulty cells 有权
标题翻译：具有故障单元的半导体存储器件
公开(公告)号：US06236601B1
公开(公告)日：2001-05-22
申请号：US09477665
申请日：2000-01-05
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C700
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.
摘要翻译：一种具有电可擦除非易失性存储器的半导体存储器件，其中非易失性存储器具有用于各个块的管理信息区域和用于登记故障地址的故障登记区域。如果一个块被访问并发现有故障，则执行故障登记，以便可以使用部分故障的存储器而不增加访问时间。此外，通过在管理信息区域中一一对应地登记用于执行块的交换的管理信息地址，并且可以根据重写的频率来交换块。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式