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41. 发明授权

US07407869B2 Method for manufacturing a free-standing substrate made of monocrystalline semiconductor material 有权
标题翻译：制造由单晶半导体材料制成的独立基板的方法
公开(公告)号：US07407869B2
公开(公告)日：2008-08-05
申请号：US11212795
申请日：2005-08-29
申请人： Bruno Ghyselen , Fabrice Letertre , Carlos Mazure
发明人： Bruno Ghyselen , Fabrice Letertre , Carlos Mazure
IPC分类号： H01L21/365
CPC分类号： C30B29/36 , H01L21/76254
摘要： A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support. A substrate of a relatively thicker layer of a third material is grown, by epitaph on the nucleation layer, to form a second assembly with the substrate attaining a sufficient thickness to be free-standing. The third material is preferably a monocrystalline material. Also, the removable character of the bonding interface is preserved with at least the substrate being heated to an epitaxial growth temperature. The coefficients of thermal expansion of the second and third materials are selected to be different from each other by a thermal expansion differential, determined as a function of the epitaxial growth temperature or subsequent application of external mechanical stresses, such that, as the second assembly cools from the epitaxial growth temperature, stresses are induced in the removable bonding interface to facilitate detachment of the nucleation layer from the substrate.
摘要翻译：一种制造由半导体材料制成的自立式基板的方法。提供了第一组件，并且其包括第一材料的相对更薄的成核层，第二材料的支撑体和限定在成核层和支撑体的相对表面之间的可去除的结合界面。通过在成核层上外延生长相对较厚的第三材料层的衬底，以形成第二组件，其中衬底获得足够的厚度以使其独立。第三种材料优选是单晶材料。而且，至少将衬底加热到外延生长温度来保存接合界面的可去除特性。第二和第三材料的热膨胀系数被选择为相互不同的热膨胀差异，其被确定为外延生长温度的函数或随后的外部机械应力的应用，使得当第二组件冷却时从外延生长温度，在可除去的结合界面中诱发应力以促进成核层与基底的分离。

42. 发明申请

US20060220129A1 Hybrid fully SOI-type multilayer structure 审中-公开
标题翻译：混合完全SOI型多层结构
公开(公告)号：US20060220129A1
公开(公告)日：2006-10-05
申请号：US11342380
申请日：2006-01-27
申请人： Fabrice Letertre , Carlos Mazure
发明人： Fabrice Letertre , Carlos Mazure
IPC分类号： H01L27/12
CPC分类号： H01L21/2007 , H01L21/76254
摘要： The invention relates to a silicon-on-insulator-type multilayer structure that includes a support layer, at least two working layers having different crystalline orientations, and an insulating layer extending over at least a portion of the support layer. This insulating layer extends over the whole surface of the support layer so as to extend completely between the support layer and the working layers. A process for manufacturing such a structure is also provided.
摘要翻译：本发明涉及一种绝缘体上硅型多层结构，其包括支撑层，至少两个具有不同结晶取向的工作层，以及在支撑层的至少一部分上延伸的绝缘层。该绝缘层在支撑层的整个表面上延伸，以便在支撑层和工作层之间完全延伸。还提供了一种用于制造这种结构的方法。

43. 发明授权

US09496877B2 Pseudo-inverter circuit with multiple independent gate transistors 有权
标题翻译：具有多个独立栅极晶体管的伪逆变器电路
公开(公告)号：US09496877B2
公开(公告)日：2016-11-15
申请号：US14346270
申请日：2011-09-30
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： H03K19/20 , G11C8/08 , G11C11/408
CPC分类号： H03K19/20 , G11C8/08 , G11C11/4085
摘要： The invention relates to a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).
摘要翻译：本发明涉及一种电路，其包括与用于施加电源电位的第一和第二端子之间的第二类型沟道的晶体管串联的第一类型沟道的晶体管，每个晶体管是至少具有多栅极晶体管第一（G1P，G1N）和第二（G2P，G2N）独立控制门，其特征在于，至少一个晶体管被配置为在施加到其第二控制栅极的第二栅极信号的作用下以耗尽模式工作（G2p，G2N）。

44. 发明申请

US20140225648A1 PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS 有权
标题翻译：具有多个独立栅极晶体管的PSEUDO-INVERTER电路
公开(公告)号：US20140225648A1
公开(公告)日：2014-08-14
申请号：US14346270
申请日：2011-09-30
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： H03K19/20
CPC分类号： H03K19/20 , G11C8/08 , G11C11/4085
摘要： The invention relates to a a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).
摘要翻译：本发明涉及一种电路，包括与用于施加电源电位的第一和第二端子之间的第二类型沟道的晶体管串联的第一类型沟道的晶体管，每个晶体管是至少具有多栅极晶体管第一（G1P，G1N）和第二（G2P，G2N）独立控制门，其特征在于，至少一个晶体管被配置为在施加到其第二控制栅极的第二栅极信号的作用下以耗尽模式工作（G2p，G2N）。

45. 发明授权

US08652887B2 Multi-layer structures and process for fabricating semiconductor devices 有权
标题翻译：用于制造半导体器件的多层结构和工艺
公开(公告)号：US08652887B2
公开(公告)日：2014-02-18
申请号：US13416813
申请日：2012-03-09
申请人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
发明人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/76254 , H01L21/02238 , H01L21/32 , H01L21/84 , H01L27/1203
摘要： The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
摘要翻译：本发明涉及一种提供绝缘体上硅（SOI）堆叠的方法，其包括衬底层，衬底层上的第一氧化物层和第一氧化物层（BOX层）上的硅层。该方法包括提供SOI堆叠的至少一个第一区域，其中通过热氧化硅层的一部分并提供SOI堆叠的至少一个第二区域来减薄硅层，其中第一氧化物层（BOX层）被稀释通过退火。

46. 发明授权

US08535996B2 Substrate having a charged zone in an insulating buried layer 有权
标题翻译：衬底在绝缘掩埋层中具有带电区域
公开(公告)号：US08535996B2
公开(公告)日：2013-09-17
申请号：US12865838
申请日：2008-03-13
申请人： Mohamad Shaheen , Frederic Allibert , Gweltaz Gaudin , Fabrice Lallement , Didier Landru , Karin Landry , Carlos Mazure
发明人： Mohamad Shaheen , Frederic Allibert , Gweltaz Gaudin , Fabrice Lallement , Didier Landru , Karin Landry , Carlos Mazure
IPC分类号： H01L21/84
CPC分类号： H01L29/78603 , H01L29/32 , H01L29/7841 , H01L31/0248
摘要： Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
摘要翻译：本发明的实施例涉及包括基底晶片，绝缘层和顶部半导体层的基板，其中绝缘层至少包括电荷密度高于1010电荷/ cm 2的绝对值的区域。本发明还涉及制造这种基材的方法。

47. 发明授权

US08384425B2 Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate 有权
标题翻译：具有埋置在绝缘体上半导体衬底的绝缘膜下方的后控制栅极的晶体管阵列
公开(公告)号：US08384425B2
公开(公告)日：2013-02-26
申请号：US12961293
申请日：2010-12-06
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H03K19/173 , H03K3/01 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11807
摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.
摘要翻译：本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上并且包括一组图案，每个图案由至少一个场效应晶体管形成，每个FET晶体管在薄膜中，源极区域，漏极区域，沟道区域和形成在沟道区域上方的前部控制栅极区域。所提供的器件还包括至少一个FET晶体管，其具有包括形成在沟道区域下方的基底衬底中的反向控制栅极区域的图案，所述背栅极区域能够被偏置以便移位晶体管的阈值电压以模拟晶体管的沟道宽度的修改或迫使晶体管保持关断或者在其前控制栅上施加的任何电压。本发明还提供了操作这种半导体器件结构的方法。

48. 发明申请

US20130029474A1 METHOD FOR TRANSFERRING A MONOCRYSTALLINE SEMICONDUCTOR LAYER ONTO A SUPPORT SUBSTRATE 有权
标题翻译：将单晶半导体层传输到支撑基板上的方法
公开(公告)号：US20130029474A1
公开(公告)日：2013-01-31
申请号：US13559396
申请日：2012-07-26
申请人： Gweltaz Gaudin , Carlos Mazure
发明人： Gweltaz Gaudin , Carlos Mazure
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.
摘要翻译：一种通过将物质注入施主衬底中将单晶半导体层转移到支撑衬底上的方法; 将施主衬底粘合到支撑衬底上; 并且将所述施主衬底压裂以将所述层转移到所述支撑衬底上; 其中待转移的单晶层的一部分变成非晶体，而不会使层的第二部分的晶格混杂，部分分别是单晶层的表面部分和掩埋部分; 并且其中非晶部分在低于500℃的温度下重结晶，其中第二部分的晶格用作用于重结晶的晶种。

49. 发明授权

US08304833B2 Memory cell with a channel buried beneath a dielectric layer 有权
标题翻译：具有埋在电介质层下方的通道的存储单元
公开(公告)号：US08304833B2
公开(公告)日：2012-11-06
申请号：US12974822
申请日：2010-12-21
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H04L27/12
CPC分类号： H01L29/7841 , H01L21/76264 , H01L21/84 , H01L27/0711 , H01L27/10802 , H01L27/1203 , H01L29/1037 , H01L29/1083 , H01L29/4236 , H01L29/66825 , H01L29/7302 , H01L29/7881
摘要： The invention provides various embodiments of a memory cell formed on a semiconductor-on-insulator (SeOI) substrate and comprising one or more FET transistors. Each FET transistor has a source region and a drain region at least portions of which are arranged in the thin layer of the SeOI substrate, a channel region in which a trench is made, and a gate region formed in the trench. Specifically, the source, drain and channel regions also have portions which are arranged also beneath the insulating layer of the SeOI substrate; the portion of channel region beneath the insulating layer extends between the portions of the source and drain regions also beneath the insulating layer; and the trench in the channel region extends into the depth of the base substrate beyond the insulating layer. Also, methods for fabricating such memory cells and memory arrays including a plurality of such memory cells.
摘要翻译：本发明提供了形成在绝缘体上半导体（SeOI）衬底上并且包括一个或多个FET晶体管的存储单元的各种实施例。每个FET晶体管具有源极区和漏极区，其至少部分布置在SeOI衬底的薄层中，其中形成沟槽的沟道区和形成在沟槽中的栅极区。具体地，源极，漏极和沟道区域还具有也被布置在SeOI衬底的绝缘层下方的部分; 绝缘层下方的沟道区域的部分在绝缘层下方的源极和漏极区的部分之间延伸; 并且沟道区域中的沟槽延伸到基底衬底的深度超过绝缘层。而且，制造这种存储单元的方法和包括多个这样的存储单元的存储器阵列。

50. 发明申请

US20120250444A1 PSEUDO-INVERTER CIRCUIT ON SeOI 有权
标题翻译： PSOUD上的PSEUDO-INVERTER电路
公开(公告)号：US20120250444A1
公开(公告)日：2012-10-04
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/08 , G05F3/02
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

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