专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20060139985A1 Non-volatile semiconductor storage device performing ROM read operation upon power-on 有权
公开(公告)号：US20060139985A1
公开(公告)日：2006-06-29
申请号：US11359898
申请日：2006-02-16
申请人： Kazushige Kanda , Hiroshi Nakamura
发明人： Kazushige Kanda , Hiroshi Nakamura
IPC分类号： G11C17/00
CPC分类号： G11C16/20 , G11C16/30
摘要： A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pads are connected to the delay circuit. Delay time in the delay time is controlled according to a chip address supplied to these two pads.

42. 发明申请

US20060120168A1 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
公开(公告)号：US20060120168A1
公开(公告)日：2006-06-08
申请号：US11337999
申请日：2006-01-24
申请人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
发明人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C7/10
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/20 , G11C16/20 , G11C16/30
摘要： A semiconductor device of this invention includes an initialization circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, and a status setting unit for setting the status of the semiconductor device to “busy” during a period in which the initialization circuit performs initialization.

43. 发明授权

US06642757B2 Semiconductor memory device having a power-on reset circuit 有权
标题翻译：具有上电复位电路的半导体存储器件
公开(公告)号：US06642757B2
公开(公告)日：2003-11-04
申请号：US09957027
申请日：2001-09-21
申请人： Tamio Ikehashi , Kazushige Kanda
发明人： Tamio Ikehashi , Kazushige Kanda
IPC分类号： H03L700
CPC分类号： H03K17/223 , G11C5/143 , G11C5/145
摘要： A semiconductor device includes an internal power supply terminal for supplying an internal power supply voltage, an oscillator generating a clock pulse when the internal power supply voltage becomes higher than a first voltage, a charge pump circuit charge pumping upon receiving the clock pulse, a reference voltage generator using the output voltage from the charge pump circuit as a power supply, and a voltage monitor which uses the output voltage from the charge pump circuit as a power supply, has a comparator for comparing a divided voltage of the internal power supply voltage with the reference voltage, and outputs a first signal of a first logic level as the power-on reset signal when the internal power supply voltage is higher than a second voltage. With this arrangement, a power-on reset circuit with little variation in power-on monitoring level can be provided.
摘要翻译：一种半导体器件包括用于提供内部电源电压的内部电源端子，当内部电源电压变得高于第一电压时产生时钟脉冲的振荡器，接收时钟脉冲时的电荷泵电路电荷泵浦，电压发生器，使用来自电荷泵电路的输出电压作为电源，以及使用来自电荷泵电路的输出电压作为电源的电压监视器，具有比较器，用于将内部电源电压的分压与参考电压，并且当内部电源电压高于第二电压时，输出第一逻辑电平的第一信号作为上电复位信号。通过这种布置，可以提供上电监视级别变化小的上电复位电路。

44. 发明授权

US06469573B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06469573B2
公开(公告)日：2002-10-22
申请号：US09731880
申请日：2000-12-08
申请人： Kazushige Kanda , Tamio Ikehashi , Ken Takeuchi , Kenichi Imamiya
发明人： Kazushige Kanda , Tamio Ikehashi , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G05F110
CPC分类号： G11C7/062
摘要： A semiconductor integrated circuit includes a limiter circuit for outputting a voltage determining flag in order to set a boosted voltage level of a booster circuit to be a predetermined value, and a monitoring circuit for monitoring a monitoring node of the limiter circuit to output a monitoring signal for the stabilization of a boosted voltage to a first external terminal. The monitoring circuit detects a first level change of the voltage determining flag from “H” to “L” after the starting of the operation of the limiter circuit, by means of a comparator, to which an external power supply voltage and external reference voltage supplied from second and third external terminals are given, and thereafter, outputs a monitoring signal for holding a constant logical level during the operation of the limiter circuit. In order to provide a voltage trimming function, a voltage intended to be set in an external terminal may be given from the outside to deactivate a feedback system of the limiter circuit to operate a resistance value of the limiter circuit to detect and store a limiter flag. Thus, there is provided a semiconductor integrated circuit capable of simply monitoring the output voltage state of an internal power supply circuit by the external terminal and easily trimming an internal voltage.
摘要翻译：半导体集成电路包括限幅电路，用于输出电压确定标志，以便将升压电路的升压电压设定为预定值;以及监视电路，用于监视限幅器电路的监视节点以输出监视信号用于稳定第一外部端子的升压电压。监控电路通过比较器检测在限制器电路的操作开始之后电压确定标志从“H”到“L”的第一电平变化，供给外部电源电压和外部参考电压给出第二和第三外部端子，然后在限幅器电路的操作期间输出用于保持恒定逻辑电平的监视信号。为了提供电压调整功能，可以从外部给出旨在设置在外部端子中的电压以去激活限幅器电路的反馈系统，以操作限幅器电路的电阻值以检测和存储限幅器标志。因此，提供了能够简单地通过外部端子监视内部电源电路的输出电压状态并容易地修整内部电压的半导体集成电路。

45. 发明授权

US06278639B1 Booster circuit having booster cell sections connected in parallel, voltage generating circuit and semiconductor memory which use such booster circuit 失效
标题翻译：具有并联连接的升压电池部分的升压电路，电压产生电路和使用这种升压电路的半导体存储器
公开(公告)号：US06278639B1
公开(公告)日：2001-08-21
申请号：US09392127
申请日：1999-09-08
申请人： Koji Hosono , Hiroshi Nakamura , Tamio Ikehashi , Kazushige Kanda , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Tamio Ikehashi , Kazushige Kanda , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C700
CPC分类号： G11C5/145
摘要： The booster circuit of the present invention includes a first booster cell section in which one or more booster cells are connected in series, and a second booster cell section having an end which is connected to the first booster cell section, in which a plurality of booster cell groups each containing one or more booster cells connected in series, are connected to each other in parallel.
摘要翻译：本发明的升压电路包括其中一个或多个升压电池串联连接的第一升压电池部分和具有连接到第一升压电池部分的端部的第二升压电池部分，其中多个增压器每个包含串联连接的一个或多个升压电池的电池组彼此并联连接。

46. 发明授权

US6097638A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6097638A
公开(公告)日：2000-08-01
申请号：US22014
申请日：1998-02-11
申请人： Toshihiko Himeno , Kazushige Kanda , Hiroshi Nakamura
发明人： Toshihiko Himeno , Kazushige Kanda , Hiroshi Nakamura
IPC分类号： G11C16/26 , G11C16/06
CPC分类号： G11C16/26
摘要： An EEPROM employs, as a scheme of detecting data of a memory cell in a memory cell array, a scheme of detecting the potential of a bit line potential sense node, which depends on the relationship in amplitude between the current for charging a bit line from a current source and the discharge current flowing to a selected cell using a sense amplifier. The sense amplifier is arranged in correspondence with one bit line and includes a constant current source transistor for charging the corresponding bit line, a latch circuit for latching memory cell data read out to the bit line potential sense node, and a switch transistor for turning on/off the charge path to the bit line based on data of the latch circuit. In the verify read mode, the cell current between the Vcc node and Vss node of a cell not to be written or a completely written cell can be turned off, so verification can be performed without flowing any unnecessary current.
摘要翻译：作为检测存储单元阵列中的存储单元的数据的方案，EEPROM采用检测位线电位检测节点的电位的方案，该方案取决于用于对位线的充电电流之间的幅度的关系，电流源和使用读出放大器流向选定单元的放电电流。读出放大器与一个位线相对应地布置，并且包括用于对相应位线充电的恒流源晶体管，用于锁存读出到位线电位检测节点的存储单元数据的锁存电路和用于导通的开关晶体管 /根据锁存电路的数据关闭位线的充电路径。在验证读取模式下，可以关闭不要写入的单元的Vcc节点和Vss节点之间的单元电流，或者完全写入单元的单元电流可以被关闭，因此可以在不流过任何不必要的电流的情况下执行验证。

47. 发明授权

US08315094B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08315094B2
公开(公告)日：2012-11-20
申请号：US12957865
申请日：2010-12-01
申请人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
发明人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.
摘要翻译：提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

48. 发明授权

US08149638B2 Semiconductor memory device and inspecting method of the same 失效
标题翻译：半导体存储器件及其检测方法
公开(公告)号：US08149638B2
公开(公告)日：2012-04-03
申请号：US12884694
申请日：2010-09-17
申请人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
发明人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C11/16 , G11C29/025 , G11C2029/1204
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells, a first decoder configured to select a first line as an inspection target from the lines, a second decoder configured to select a second line for generating a reference voltage from the lines, a driver configured to charge the first and second lines, a discharging circuit configured to simultaneously discharge the first and second lines, and a sense amplifier configured to compare a voltage of the first line with a voltage of the second line to detect a defect of the first line while the first line is discharged.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，其包括存储单元，提供用于对应于存储单元的线，第一解码器，被配置为从线选择第一行作为检查对象;第二解码器，被配置为选择用于从所述线路产生参考电压的第二线路，被配置为对所述第一和第二线路充电的驱动器，配置成同时对所述第一和第二线路进行放电的放电电路;以及读出放大器，被配置为将所述第一线路的电压与第一线的电压在第一线放电时检测第一线的缺陷。

49. 发明申请

US20110103135A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO 有权
标题翻译：非易失性存储器件及其数据写入方法
公开(公告)号：US20110103135A1
公开(公告)日：2011-05-05
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

50. 发明授权

US07646222B2 Semiconductor device for generating power on reset signal 失效
标题翻译：用于产生上电复位信号的半导体器件
公开(公告)号：US07646222B2
公开(公告)日：2010-01-12
申请号：US11376416
申请日：2006-03-16
申请人： Masaki Ichikawa , Kazushige Kanda
发明人： Masaki Ichikawa , Kazushige Kanda
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24
摘要： A reference voltage generating circuit receives a power supply voltage and generates a reference voltage. A reference voltage level guarantee circuit generates a sense signal when the circuit senses that a value of the reference voltage has reached a predetermined value. A power supply voltage sensing circuit has a voltage comparator circuit which compares a voltage obtained by dividing a power supply voltage with the reference voltage and outputs a power ON reset signal. An operation of the voltage comparator circuit is controlled based on a sense signal. When the value of the power supply voltage increases and the value of the reference voltage reaches a predetermined value, the voltage comparator circuit operates, and a power ON reset signal is outputted in response to a result of comparison between a divisional voltage and the reference voltage.
摘要翻译：参考电压产生电路接收电源电压并产生参考电压。当电路感测到参考电压的值已经达到预定值时，参考电压电平保证电路产生感测信号。电源电压检测电路具有电压比较器电路，其将通过将电源电压分压获得的电压与参考电压进行比较，并输出电源接通复位信号。基于感测信号来控制电压比较器电路的操作。当电源电压值增加并且参考电压的值达到预定值时，电压比较器电路工作，并且响应于分压与参考电压之间的比较结果而输出电源复位信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式