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41. 发明申请

US20110029654A1 Service Control Device, Service Control System, and Method 有权
标题翻译：服务控制装置，服务控制系统和方法
公开(公告)号：US20110029654A1
公开(公告)日：2011-02-03
申请号：US12866396
申请日：2008-12-19
申请人： Yukiko Takeda , Akihiko Takase , Daisuke Matsubara
发明人： Yukiko Takeda , Akihiko Takase , Daisuke Matsubara
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L51/066 , H04L65/1006 , H04L65/105 , H04L65/1083 , H04L65/40 , H04L67/02 , H04M3/50 , H04M7/003 , H04M2203/2016
摘要： A communication entrepreneur has an application server 2 having message conversion function. The application server 2 performs service function distribution processing with reference to trigger rule 220 and message rule 230. The communication entrepreneur can provide various service functions without notifying individual server addresses to a service entrepreneur.
摘要翻译：通信企业家具有具有消息转换功能的应用服务器2。应用服务器2参照触发规则220和消息规则230执行服务功能分配处理。通信企业家可以提供各种服务功能，而不向服务企业家通知各个服务器地址。

42. 发明申请

US20080008091A1 Qos CONTROL SYSTEM 审中-公开
标题翻译： QOS控制系统
公开(公告)号：US20080008091A1
公开(公告)日：2008-01-10
申请号：US11764400
申请日：2007-06-18
申请人： Kazuma Yumoto , Akihiko Takase
发明人： Kazuma Yumoto , Akihiko Takase
IPC分类号： H04L12/56
CPC分类号： H04L47/24 , H04L47/15 , H04L47/70 , H04L47/745 , H04L47/748 , H04L47/781 , H04L47/822 , H04L47/824
摘要： A QoS control system for controlling allocation of a resource in a network, comprising: a terminal unit; a node unit for transferring a packet which is sent and to be received by the terminal unit; a resource requesting unit for requesting to allocate of a resource of the node unit; and a QoS control unit for controlling allocation of a resource of the node unit; in which the QoS control unit manages communication path information for transferring the packet received by the node unit, and resource information of the node unit, determines whether or not a node unit included in the communication path through which the terminal unit makes a communication can provide with a requested resource, and determines an alternative proposal of the requested resource when the node unit cannot provide with the requested resource, and notifies the resource requesting unit of the alternative proposal.
摘要翻译：一种用于控制网络中的资源分配的QoS控制系统，包括：终端单元; 节点单元，用于传送由终端单元发送和要接收的分组; 资源请求单元，用于请求分配节点单元的资源; 以及QoS控制单元，用于控制所述节点单元的资源的分配; 其中QoS控制单元管理用于传送由节点单元接收的分组的通信路径信息和节点单元的资源信息，确定包括在终端单元进行通信的通信路径中的节点单元是否可以提供并且当节点单元不能提供所请求的资源时，确定所请求的资源的替代方案，并且向资源请求单元通知替代提议。

43. 发明授权

US06993029B2 IP switch, interface circuit and ATM switch used for IP switch, and IP switch network system 失效
公开(公告)号：US06993029B2
公开(公告)日：2006-01-31
申请号：US10370285
申请日：2003-02-19
申请人： Tetsuro Yoshimoto , Kazuho Miki , Akihiko Takase
发明人： Tetsuro Yoshimoto , Kazuho Miki , Akihiko Takase
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04Q11/0478 , H04L12/4608 , H04L12/5601 , H04L49/3081 , H04L69/22 , H04L2012/5619 , H04L2012/5627 , H04L2012/563 , H04L2012/5632 , H04L2012/5642 , H04L2012/5645 , H04L2012/5647 , H04L2012/5649 , H04L2012/5658 , H04L2012/5667
摘要： In a system in which communication is performed among a plurality of devices having a mechanism of disassembling a packet into ATM cells to send them and a plurality of devices having a mechanism of assembling the received ATM cells into the packet, a frame is prevented from being lost owing to change of virtual connections in the course of transferring the frame, improving reliability of the communication on the packet level. When the switch receives a request for change of switching, it does not processes that request at once, but confirms that the cell located at the boundary of the frame has been processed, before processing the change request, so as to protect the frame. When the switch receives a request for change of switching, it protects a frame by multicasting the cells to both destinations before change and after change, for a given period of time.

44. 发明授权

US06980553B2 Router apparatus using ATM switch 失效
标题翻译：路由器使用ATM交换机
公开(公告)号：US06980553B2
公开(公告)日：2005-12-27
申请号：US10152836
申请日：2002-05-23
申请人： Kazuho Miki , Masahiro Takatori , Akihiko Takase , Masaru Murakami , Koji Wakayama , Tetsuro Yoshimoto , Masao Kunimoto
发明人： Kazuho Miki , Masahiro Takatori , Akihiko Takase , Masaru Murakami , Koji Wakayama , Tetsuro Yoshimoto , Masao Kunimoto
IPC分类号： H04J3/04 , H04L12/28 , H04L12/56 , H04L12/66
CPC分类号： H04L49/25 , H04L12/5601 , H04L49/3072 , H04L49/602 , H04L49/606 , H04L2012/5667 , H04L2012/567
摘要： A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.
摘要翻译：路由器装置5具有ATM交换机，用于执行路由控制的IP控制器作为层3的控制器，分别提供给执行各种通信的多个传输路径的多种接口以及信元复用/解复用并且基于识别信息管理各个部分之间的小区通信。输入分组在接口中进行IP处理，以公共格式转换为小区，并且该小区基于小区从另一接口的小区被串行多路复用，并在小区多路复用/ 解复用单元。每个接口和每个信元复用/解复用单元通过使用登记有识别信息的对应关系的表来设置和切换用于报文的报头部分的标识信息和要传送的小区。

45. 发明授权

US06526045B2 IP switch, interface circuit and ATM switch used for IP switch, and IP switch network system 失效
标题翻译： IP交换机，接口电路和ATM交换机用于IP交换机，IP交换网络系统
公开(公告)号：US06526045B2
公开(公告)日：2003-02-25
申请号：US09776283
申请日：2001-02-02
申请人： Tetsuro Yoshimoto , Kazuho Miki , Akihiko Takase
发明人： Tetsuro Yoshimoto , Kazuho Miki , Akihiko Takase
IPC分类号： H04L1256
CPC分类号： H04Q11/0478 , H04L12/4608 , H04L12/5601 , H04L49/3081 , H04L69/22 , H04L2012/5619 , H04L2012/5627 , H04L2012/563 , H04L2012/5632 , H04L2012/5642 , H04L2012/5645 , H04L2012/5647 , H04L2012/5649 , H04L2012/5658 , H04L2012/5667
摘要： In a system in which communication is performed among a plurality of devices having a mechanism of disassembling a packet into ATM cells to send them and a plurality of devices having a mechanism of assembling the received ATM cells into the packet, a frame is prevented from being lost owing to change of virtual connections in the course of transferring the frame, improving reliability of the communication on the packet level. When the switch receives a request for change of switching, it does not processes that request at once, but confirms that the cell located at the boundary of the frame has been processed, before processing the change request, so as to protect the frame. When the switch receives a request for change of switching, it protects a frame by multicasting the cells to both destinations before change and after change, for a given period of time.
摘要翻译：在具有将分组拆分为ATM信元以发送它们的机制的多个设备之间进行通信的系统和具有将接收的ATM信元组装到分组中的机构的多个设备中，防止帧被由于传输帧过程中虚拟连接的变化而丢失，提高了分组级通信的可靠性。当交换机接收到切换更改请求时，它不会立即处理该请求，但确认该小区在处理变化请求之前已经处理了帧的边界，以便保护帧。当交换机接收到切换改变的请求时，它在改变之前和之后通过将信元组播到两个目的地来保护帧改变，在一段给定的时间内。

46. 发明授权

US06463066B2 ATM switch 失效
标题翻译： ATM交换机
公开(公告)号：US06463066B2
公开(公告)日：2002-10-08
申请号：US09797696
申请日：2001-03-05
申请人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
发明人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
IPC分类号： H04J324
CPC分类号： H04L49/108 , H04Q11/0478
摘要： Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.
摘要翻译：提供了一种高吞吐量大容量ATM交换机，其中在将DRAM用作ATM交换机的小区缓冲器的情况下产生的存储器访问时间和数据输出延迟时间的变化被吸收。为了实现这一点，ATM交换机包括使用用于存储单元的DRAM的第一存储器，使用SRAM的第二存储器，用于在将单元传送到第一存储器之前切换和临时存储单元;以及控制器，用于产生写/ 用于第一和第二存储器的定时信号。控制器产生用于第二存储器的读取地址和定时信号，并且基于第一存储器的存取地址来考虑第一存储器的存取时间或延迟时间的变化的写入地址和定时信号，从而在目的地输出将单元切换并存储在第二存储器中，然后存储在第一存储器中。

47. 发明授权

US6034954A Multiplexing apparatus for transit of signals between service provided by low-speed transmission path and ATM service provided by high-speed transmission path 失效
标题翻译：由低速传输路径提供的服务之间的信号传输和由高速传输路径提供的ATM服务的多路复用装置
公开(公告)号：US6034954A
公开(公告)日：2000-03-07
申请号：US912057
申请日：1997-08-15
申请人： Akihiko Takase , Masahiro Takatori , Masaru Murakami , Kaori Nakayama , Hitoshi Yajima , Takaaki Toyama
发明人： Akihiko Takase , Masahiro Takatori , Masaru Murakami , Kaori Nakayama , Hitoshi Yajima , Takaaki Toyama
IPC分类号： H04J3/04 , H04L12/28 , H04L12/951 , H04Q3/00 , H04Q11/04 , H04L12/56
CPC分类号： H04L12/5692 , H04L49/3081 , H04Q11/0478 , H04L2012/5658
摘要： For reducing the scale of a multiplexer, a lower speed ATM interface block, an interface block for SDT mode circuit emulation, and an interface block for UDT mode circuit emulation perform processing for terminating services provided by lower speed transmission lines accommodated therein, and part of AAL processing, which is pre-processing depending on a service, for generating ATM cells from signals received by a terminated service, and send the processed signal to a higher speed line interface using a previously assigned time slot on a time-division bus. The higher speed line interface once stores the signals received from the time-division bus in a buffer, and subsequently performs certain processing including a common portion for respective signals for generating therefrom ATM cells in which the signals are stored in payloads. The generated ATM cells are multiplexed and transmitted onto a higher speed transmission line.
摘要翻译：为了减少多路复用器的规模，低速ATM接口块，用于SDT模式电路仿真的接口块和用于UDT模式电路仿真的接口块执行用于终止由其中容纳的低速传输线提供的服务的处理，并且部分 AAL处理，其是根据服务进行的预处理，用于由终止的服务接收的信号产生ATM信元，并且使用时分总线上的先前分配的时隙将处理的信号发送到更高速线路接口。较高速度线路接口一次将从时分总线接收的信号存储在缓冲器中，并且随后执行包括用于从其生成的相应信号的公共部分的某些处理，其中信号被存储在有效载荷中的ATM信元。所生成的ATM信元被复用并发送到更高速的传输线上。

48. 发明授权

US5963555A Router apparatus using ATM switch 失效
公开(公告)号：US5963555A
公开(公告)日：1999-10-05
申请号：US923873
申请日：1997-09-02
申请人： Akihiko Takase , Masahiro Takatori , Kazuho Miki , Masaru Murakami , Koji Wakayama , Tetsuro Yoshimoto , Masao Kunimoto
发明人： Akihiko Takase , Masahiro Takatori , Kazuho Miki , Masaru Murakami , Koji Wakayama , Tetsuro Yoshimoto , Masao Kunimoto
IPC分类号： H04Q3/00 , H04L12/773 , H04L12/801 , H04L12/815 , H04L12/911 , H04Q11/04 , H04L12/66
CPC分类号： H04L12/5601 , H04L49/255 , H04L49/606 , H04L49/608 , H04Q11/0478 , H04L2012/5618 , H04L2012/5638 , H04L2012/5652 , H04L2012/5658 , H04L2012/5667 , H04L2012/5674 , H04L2012/5681
摘要： An LAN interface unit and an ATM switch unit cooperate to perform traffic control. A QoS unit monitors circumstances of an input buffer from a multiplexer of the ATM switch by means of a system controller and when an overflow of the input buffer is expected, the LAN interface unit of the multiplexer is instructed to perform traffic control. The LAN interface unit performs traffic control such as limitation of ATM cells inputted in the ATM switch.

49. 发明授权

US5828654A ATM cell policing method and apparatus 失效
标题翻译： ATM信元监管方法和装置
公开(公告)号：US5828654A
公开(公告)日：1998-10-27
申请号：US653475
申请日：1996-05-24
申请人： Akihiko Takase , Shigeo Shinada , Mitsuhiro Takano , Toshiya Oouchi , Naoaki Yamanaka , Youichi Sato
发明人： Akihiko Takase , Shigeo Shinada , Mitsuhiro Takano , Toshiya Oouchi , Naoaki Yamanaka , Youichi Sato
IPC分类号： H04L12/813 , H04Q11/04 , H04J3/14
CPC分类号： H04L12/5602 , H04L49/3081 , H04Q11/0478 , H04L2012/5636 , H04L2012/5651
摘要： In an input cell policing method in a network of an asynchronous transfer mode, according to information contained in a header field of each input cell, a group to which the cell belongs is identified. For each group, there are set a plurality of time frames having a predetermined length and mutually different phases to count the number of input cells in each time frame period. For each time frame, the count value of input cells is compared with a predetermined threshold value. An input cell for which the count value exceeds the threshold value in either one of the time frames is assumed to be an excess cell. The excess cell is discarded or a violation mark is added thereto.
摘要翻译：在异步传输模式的网络中的输入单元监管方法中，根据包含在每个输入单元的报头字段中的信息，识别该单元所属的组。对于每个组，设置具有预定长度和相互不同相位的多个时间帧以对每个时间段中的输入单元的数量进行计数。对于每个时间帧，将输入单元的计数值与预定阈值进行比较。在任一时间帧中计数值超过阈值的输入单元被假设为过剩单元。丢弃多余的单元格或向其中添加违规标记。

50. 发明授权

US5694554A ATM interface and shaping method 失效
标题翻译： ATM接口和整形方法
公开(公告)号：US5694554A
公开(公告)日：1997-12-02
申请号：US521994
申请日：1995-08-31
申请人： Kaori Kawabata , Tatsuo Mochinaga , Akihiko Takase
发明人： Kaori Kawabata , Tatsuo Mochinaga , Akihiko Takase
IPC分类号： H04J3/06 , H04L12/70 , H04Q11/04 , H04L12/56 , H04J3/02
CPC分类号： H04J3/0632 , H04Q11/0478 , H04L2012/568 , H04L2012/5681
摘要： In a shaping method of controlling interval of transmission of cells to a transmission path, an input cell is temporarily accumulated in a buffer memory such that transmission time of the input cell is decided according to a traffic condition beforehand registered for each VPI and a traffic condition registered in advance for each VPI/VCI. The conditions are stored in a parameter table. The transmission time is compared with transmission time assigned to each of the preceding cells accumulated in the buffer memory. If conflict occurs therebetween, the transmission time is corrected and then correspondence between the transmission time and identifying information of the input cell are stored in an output control memory. Referring to the memory, the cells are read from the buffer memory in the sequence of transmission time to be sent to an output communication line.
摘要翻译：在控制传送到传输路径的小区传输间隔的整形方法中，输入单元临时地累积在缓冲存储器中，使得根据预先为每个VPI注册的业务条件和业务条件确定输入小区的传输时间为每个VPI / VCI提前注册。条件存储在参数表中。将传输时间与分配给在缓冲存储器中累积的每个先前单元的传输时间进行比较。如果在它们之间发生冲突，则校正传输时间，然后将传输时间和输入单元的识别信息之间的对应关系存储在输出控制存储器中。参考存储器，以传输时间的顺序从缓冲存储器读取单元，以将其发送到输出通信线路。

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