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41. 发明授权

US08043945B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08043945B2
公开(公告)日：2011-10-25
申请号：US12401453
申请日：2009-03-10
申请人： Ichiro Mizushima , Shinji Mori , Masahiko Murano , Tsutomu Sato , Takashi Nakao , Hiroshi Itokawa
发明人： Ichiro Mizushima , Shinji Mori , Masahiko Murano , Tsutomu Sato , Takashi Nakao , Hiroshi Itokawa
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02636 , H01L21/02381 , H01L21/02532 , H01L21/0262
摘要： A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.
摘要翻译：根据一个实施例的制造半导体器件的方法包括：将半导体衬底的表面暴露于含有Si和Ge中的至少一种的含卤素的气体，所述半导体衬底设置有包含氧化物的构件，主要由的Si; 以及将半导体衬底的表面开始暴露于含卤素气体之后，将半导体衬底的表面暴露于含有不含卤素的含Si气体和不含卤素的含Ge气体中的至少一种的气氛中，从而在表面上外延生长含有Si和Ge中的至少一种的晶体膜。

42. 发明授权

US08017989B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08017989B2
公开(公告)日：2011-09-13
申请号：US12659703
申请日：2010-03-17
申请人： Yoshio Ozawa , Ichiro Mizushima , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi
发明人： Yoshio Ozawa , Ichiro Mizushima , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.
摘要翻译：一种非易失性半导体存储器件，包括具有半导体层和设置在其表面上的绝缘材料的半导体衬底，绝缘材料的表面被半导体层覆盖，并且设置在半导体层上的多个存储单元，存储器电池包括通过覆盖半导体层的表面而提供的第一电介质膜，设置在绝缘材料上方和第一电介质膜上的多个电荷存储层，设置在每个电荷存储层上的多个第二电介质膜，多个设置在每个第二电介质膜上的导电层，以及杂质扩散层，其部分或整体形成在绝缘材料的至少上方和半导体层的内部，并且其底端的至少一部分由绝缘体的上表面材料。

43. 发明授权

US08012858B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08012858B2
公开(公告)日：2011-09-06
申请号：US12560265
申请日：2009-09-15
申请人： Masahiko Murano , Ichiro Mizushima , Tsutomu Sato , Shinji Mori , Shuji Katsui , Hiroshi Itokawa
发明人： Masahiko Murano , Ichiro Mizushima , Tsutomu Sato , Shinji Mori , Shuji Katsui , Hiroshi Itokawa
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/02378 , H01L21/02532 , H01L21/02661 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/66795 , H01L29/7848
摘要： A method of fabricating a semiconductor device according to one embodiment includes: removing a native oxide film and adhering silicon nitrides on an area of a Si based substrate in hydrogen gas atmosphere under a condition in which a pressure is a first pressure and a temperature is a first temperature, a silicon nitride-containing member being formed on the Si based substrate, the area being a area not covered by the member; lowering the temperature to a second temperature from the first temperature while maintaining the pressure at the first pressure in hydrogen gas atmosphere; lowering the pressure to a second pressure from the first pressure while maintaining the temperature at the second temperature in hydrogen gas atmosphere; and epitaxially growing a crystal on the area of the Si based substrate in a precursor gas atmosphere after the pressure is lowered to the second pressure, the crystal including at least one of Si and Ge, the precursor gas atmosphere including at least one of hydrogen, Si and Ge.
摘要翻译：根据一个实施例的制造半导体器件的方法包括：在氢气气氛中，在压力为第一压力和温度为的条件下，除去天然氧化物膜并将硅氮化物粘附在Si基衬底的区域上第一温度，在所述Si基衬底上形成含氮化硅的构件，所述区域是未被构件覆盖的区域; 将温度从第一温度降低到第二温度，同时保持在氢气气氛中的第一压力下的压力; 将压力从第一压力降低到第二压力，同时将温度保持在第二温度在氢气气氛中; 并且在所述压力降低到所述第二压力之后，在前驱体气体气氛中，在所述Si基基板的区域上外延生长晶体，所述晶体包括Si和Ge中的至少一种，所述前体气体气体包括氢， Si和Ge。

44. 发明申请

US20110049611A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：非挥发性半导体存储器件的非线性半导体存储器件的制造方法和非易失性半导体存储器件的制造方法
公开(公告)号：US20110049611A1
公开(公告)日：2011-03-03
申请号：US12769951
申请日：2010-04-29
申请人： Masahiro Kiyotoshi , Atsuhiro Kinoshita , Kiwamu Sakuma , Koichi Muraoka , Ichiro Mizushima
发明人： Masahiro Kiyotoshi , Atsuhiro Kinoshita , Kiwamu Sakuma , Koichi Muraoka , Ichiro Mizushima
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11526 , H01L27/11529 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881
摘要： In a memory cell portion, a stacked structure, in which dielectric layers and semiconductor layers are alternately stacked, is arranged in a fin shape on a semiconductor substrate, and in a peripheral circuit portion, a gate electrode is arranged on the semiconductor substrate via a gate dielectric film so that a height of an upper surface of the gate electrode is set to be substantially equal to a height of an upper surface of the stacked structure in which the dielectric layers and the semiconductor layers are alternately stacked.
摘要翻译：在存储单元部分中，电介质层和半导体层交替层叠的堆叠结构在半导体衬底上以翅片形状布置，并且在外围电路部分中，栅电极经由使得栅极电极的上表面的高度被设定为与电介质层和半导体层交替层叠的层叠结构的上表面的高度大致相等。

45. 发明授权

US07718483B2 Method of manufacturing non-volatile semiconductor memory 失效
标题翻译：制造非易失性半导体存储器的方法
公开(公告)号：US07718483B2
公开(公告)日：2010-05-18
申请号：US11399655
申请日：2006-04-07
申请人： Ichiro Mizushima , Hajime Nagano , Yoshio Ozawa , Hisataka Meguro , Takashi Suzuki
发明人： Ichiro Mizushima , Hajime Nagano , Yoshio Ozawa , Hisataka Meguro , Takashi Suzuki
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/1052 , H01L27/11521
摘要： In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.
摘要翻译：在根据本发明的用于制造非易失性半导体器件的方法中，提供了用于在衬底上形成多个第一半导体部分的步骤; 选择性地生长与所述多个第一半导体部分接触的多个第二半导体部分; 部分地去除所述多个第二半导体部分以制备具有基本平坦表面的多个浮动栅极; 在所述多个浮动栅极上形成绝缘层; 以及在所述绝缘层上形成控制栅极。

46. 发明授权

US07602013B2 Semiconductor device with recessed channel 失效
标题翻译：带凹槽的半导体器件
公开(公告)号：US07602013B2
公开(公告)日：2009-10-13
申请号：US11649752
申请日：2007-01-05
申请人： Kiyotaka Miyano , Ichiro Mizushima , Kouji Matsuo
发明人： Kiyotaka Miyano , Ichiro Mizushima , Kouji Matsuo
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/30625 , H01L21/324 , H01L29/165 , H01L29/4916 , H01L29/495 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/66621
摘要： A semiconductor device includes: a layer provided on or above a semiconductor substrate, having an opening, and containing Si and Ge; and a gate provided at a position corresponding to the opening. It is possible to provide a semiconductor device and a manufacturing method of the same which realize easy control of a recess amount and reduction in damage at the time of the recessing.
摘要翻译：半导体器件包括：设置在半导体衬底上或上方的具有开口并且包含Si和Ge的层; 以及设置在与开口相对应的位置处的门。可以提供一种半导体器件及其制造方法，其实现容易控制凹陷量并减少凹陷时的损伤。

47. 发明申请

US20090011570A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090011570A1
公开(公告)日：2009-01-08
申请号：US12146143
申请日：2008-06-25
申请人： Ichiro Mizushima , Yoshio Ozawa , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi , Minako Inukai , Kaori Umezawa , Hiroaki Yamada
发明人： Ichiro Mizushima , Yoshio Ozawa , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi , Minako Inukai , Kaori Umezawa , Hiroaki Yamada
IPC分类号： H01L21/76
CPC分类号： H01L21/764
摘要： A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.
摘要翻译：一种制造半导体器件的方法包括：去除半导体衬底的一部分以在半导体衬底的表面区域中形成突出部分和凹陷部分，在凹部中形成第一外延半导体层，形成第二外延半导体层在所述突出部分和所述第一外延半导体层上，用所述第二外延半导体层的第二部分去除所述第二外延半导体层的第一部分，以露出所述第一外延半导体层的一部分，并且蚀刻所述第一外延半导体层从第一外延半导体层的暴露部分形成在第二外延半导体层的第二部分下面的空腔。

48. 发明申请

US20080224252A1 Semiconductor device having an element isolating insulating film 有权
标题翻译：具有元件隔离绝缘膜的半导体器件
公开(公告)号：US20080224252A1
公开(公告)日：2008-09-18
申请号：US12068635
申请日：2008-02-08
申请人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
发明人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
IPC分类号： H01L29/00
CPC分类号： H01L21/28194 , H01L21/28088 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/76262 , H01L21/823481 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545
摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
摘要翻译：在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸，以防止形成小平面。随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

49. 发明申请

US20070293027A1 DOPANT DIFFUSION METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译： DOPANT扩散方法及制造半导体器件的方法
公开(公告)号：US20070293027A1
公开(公告)日：2007-12-20
申请号：US11687315
申请日：2007-03-16
申请人： Takuya Konno , Ichiro Mizushima , Takashi Suzuki , Nobuaki Makino
发明人： Takuya Konno , Ichiro Mizushima , Takashi Suzuki , Nobuaki Makino
IPC分类号： H01L21/223
CPC分类号： H01L21/223
摘要： A dopant diffusion method includes: diffusing a dopant element into a semiconductor through an oxide film. The dopant element is contained in a compound gas having a gas partial pressure of not less than 0.1 torr and not more than 800 torr. A temperature of the semiconductor is set less than 750° C. and not more than 950° C. A method of manufacturing a semiconductor device including a semiconductor with a dopant element diffused therein, the method includes: diffusing a dopant element into the semiconductor through an oxide film. The dopant element is contained in a compound gas having a gas partial pressure of not less than 0.1 torr and not more than 800 torr, and a temperature of the semiconductor is set less than 750° C. and not more than 950° C.
摘要翻译：掺杂剂扩散方法包括：通过氧化物膜将掺杂剂元素扩散到半导体中。掺杂剂元素包含在气体分压不小于0.1托且不大于800托的复合气体中。半导体的温度设定为小于750℃且不高于950℃。一种制造半导体器件的方法，该半导体器件包括其中扩散掺杂剂元素的半导体，该方法包括：将掺杂元素扩散到半导体中，通过氧化膜。掺杂剂元素含有气体分压为0.1托以上800托以下的复合气体，半导体的温度设定为小于750℃，不高于950℃。

50. 发明授权

US07265017B2 Method for manufacturing partial SOI substrates 失效
标题翻译：制造部分SOI衬底的方法
公开(公告)号：US07265017B2
公开(公告)日：2007-09-04
申请号：US11168914
申请日：2005-06-29
申请人： Hajime Nagano , Ichiro Mizushima
发明人： Hajime Nagano , Ichiro Mizushima
IPC分类号： H01L21/331
CPC分类号： H01L27/1203 , H01L21/84
摘要： There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region and the non-SOI region and having a second insulating film buried therein, the second insulating film being inclined upward from the SOI region side toward the non-SOI region side, the second insulating film having a thickness smaller than the thickness of the first insulating film and being tapered from the SOI region side to the non-SOI region side, a pair of element isolating insulating regions separately formed in the non-SOI region of semiconductor substrate and defining element regions, a pair of impurity diffusion regions formed in the element regions, and a gate electrode formed via a gate insulating film in the element region of the semiconductor substrate.
摘要翻译：封闭半导体器件，其包括半导体衬底，该半导体衬底包括掩埋有第一绝缘膜的SOI区域和非SOI区域，该半导体衬底设置有形成在SOI区域与非SOI区域之间的边界区域并且具有埋置在其中的第二绝缘膜，所述第二绝缘膜从所述SOI区域侧向非SOI区域侧向上倾斜，所述第二绝缘膜的厚度小于所述第一绝缘膜的厚度， SOI区域侧，分离地形成在半导体衬底的非SOI区域中并限定元件区域的一对元件隔离绝缘区域，形成在元件区域中的一对杂质扩散区域以及栅极电极通过半导体衬底的元件区域中的栅极绝缘膜形成。

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