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41. 发明申请

US20120061759A1 Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same 有权
标题翻译：极薄的绝缘体上半导体（ETSOI）FET，具有阶梯式引出源/漏极及其形成方法
公开(公告)号：US20120061759A1
公开(公告)日：2012-03-15
申请号：US12882490
申请日：2010-09-15
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L29/786 , H01L21/782
CPC分类号： H01L29/78654 , H01L29/66628 , H01L29/66772
摘要： A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.
摘要翻译：在具有厚度范围为3nm至20nm的半导体层的绝缘体上半导体（SOI）衬底的顶部上形成MOSFET器件。在SOI衬底的顶部上形成阶梯形凸起的延伸部，凸起的源极区域和凸起的漏极区域（S / D）。更薄的凸起的延伸区域邻近薄的栅极侧壁间隔物，降低延伸电阻而不显着增加寄生电阻。单个外延生长优选同时形成更薄的凸起延伸和较高的凸起S / D，从而降低制造成本以及升高的S / D与延伸部之间的接触电阻。还提供了形成上述MOSFET器件的方法。

42. 发明申请

US20120049284A1 Same-Chip Multicharacteristic Semiconductor Structures 有权
标题翻译：同芯多特征半导体结构
公开(公告)号：US20120049284A1
公开(公告)日：2012-03-01
申请号：US12861976
申请日：2010-08-24
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L27/1211 , H01L27/1203
摘要： In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.
摘要翻译：在一个示例性实施例中，半导体结构包括：绝缘体上半导体衬底，具有覆盖绝缘层的顶部半导体层，绝缘层覆盖在底部衬底层上; 至少一个第一装置至少部分地覆盖并设置在顶部半导体层的第一部分上，其中第一部分具有第一厚度，第一宽度和第一深度; 以及至少一个第二装置，其至少部分地覆盖并设置在顶部半导体层的第二部分上，其中第二部分具有第二厚度，第二宽度和第二深度，其中以下至少一个成立：第一厚度大于第二厚度，第一宽度大于第二宽度，第一深度大于第二深度。

43. 发明授权

US08124470B1 Strained thin body semiconductor-on-insulator substrate and device 有权
标题翻译：应变薄体绝缘体上半导体衬底和器件
公开(公告)号：US08124470B1
公开(公告)日：2012-02-28
申请号：US12892950
申请日：2010-09-29
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/76283 , H01L29/66772 , H01L29/7842 , H01L29/7847 , H01L29/78603
摘要： A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress. An active device semiconductor layer is formed over the second semiconductor layer such that the active device semiconductor layer is initially in a relaxed state. One or more trench isolation structures are formed through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress.
摘要翻译：形成应变绝缘体上半导体衬底的方法包括在第一半导体衬底上形成第二半导体层。第二半导体与第一半导体衬底晶格匹配，使得第二半导体层经受第一定向应力。在第二半导体层上形成有源器件半导体层，使得有源器件半导体层初始处于松弛状态。通过有源器件层和通过第二半导体层形成一个或多个沟槽隔离结构，以便使有源器件层下方的第二半导体层松弛，并在与第一方向应力相反的有源器件层上施加第二方向应力。

44. 发明申请

US20120043623A1 METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE 有权
标题翻译：在绝缘体器件上形成高K /金属栅极极微电子半导体的方法与结构
公开(公告)号：US20120043623A1
公开(公告)日：2012-02-23
申请号：US12859414
申请日：2010-08-19
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/28114 , H01L29/165 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/78 , H01L29/7848
摘要： A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.
摘要翻译：提供一种半导体器件，其包括存在于衬底上的栅极结构。所述栅极结构包括栅极导体，所述栅极导体在所述栅极导体的第一部分的侧壁中具有底切区域，其中所述栅极导体的第二部分存在于所述栅极导体的所述第一部分之上并且包括在所述底切区域上方的突出部分。间隔件邻近门结构的侧壁，其中间隔件包括填充底切区域的延伸部分。凸起的源极区域和隆起的漏极区域邻近间隔物存在。升高的源极区域和隆起的漏极区域通过间隔物的延伸部分与栅极导体分离。

45. 发明申请

US20120025282A1 Raised Source/Drain Field Effect Transistor 有权
公开(公告)号：US20120025282A1
公开(公告)日：2012-02-02
申请号：US12848494
申请日：2010-08-02
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/94 , H01L27/088 , H01L21/336 , H01L27/105
CPC分类号： H01L27/1203 , H01L21/823418 , H01L21/823425 , H01L21/84 , H01L29/66628
摘要： In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.

46. 发明申请

US20110309446A1 STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER 有权
标题翻译：具有单个间距的垂直源/源压应力的应变薄体CMOS器件
公开(公告)号：US20110309446A1
公开(公告)日：2011-12-22
申请号：US12816399
申请日：2010-06-16
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/8238 , H01L29/786 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译：一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一在图案化的栅极结构下方的半导体衬底的沟道区上。

47. 发明申请

US20110254080A1 TUNNEL FIELD EFFECT TRANSISTOR 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US20110254080A1
公开(公告)日：2011-10-20
申请号：US12760287
申请日：2010-04-14
申请人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.
摘要翻译：公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。形成覆盖栅极堆叠和结的硬掩模。执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。去除硬掩模的注入部分，并露出其中一个接头。该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

48. 发明申请

US20110227165A1 HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE 有权
公开(公告)号：US20110227165A1
公开(公告)日：2011-09-22
申请号：US13151525
申请日：2011-06-02
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
IPC分类号： H01L27/092
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/1054 , H01L29/66795
摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

49. 发明授权

US08022488B2 High-performance FETs with embedded stressors 有权
标题翻译：具有嵌入式应力的高性能FET
公开(公告)号：US08022488B2
公开(公告)日：2011-09-20
申请号：US12566004
申请日：2009-09-24
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/02
CPC分类号： H01L29/7848 , H01L21/2257 , H01L21/26586 , H01L29/165 , H01L29/41775 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.
摘要翻译：提供了高性能半导体结构和制造这种结构的方法。半导体结构包括位于半导体衬底的上表面上的至少一个栅堆叠，例如FET。该结构还包括在至少一个栅极堆叠的沟道上引起应变的第一外延半导体材料。第一外延半导体材料位于至少一个栅极堆叠的基准面上，基本上位于衬底中的存在于至少一个栅极堆叠的相对侧上的一对凹陷区域内。扩散扩展区域位于每个凹陷区域中的所述第一外延半导体材料的上表面内。该结构还包括位于扩散扩展区的上表面上的第二外延半导体材料。第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

50. 发明授权

US07993999B2 High-K/metal gate CMOS finFET with improved pFET threshold voltage 有权
标题翻译：高K /金属栅极CMOS finFET，具有改善的pFET阈值电压
公开(公告)号：US07993999B2
公开(公告)日：2011-08-09
申请号：US12614906
申请日：2009-11-09
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
IPC分类号： H01L21/8238
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/1054 , H01L29/66795
摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.
摘要翻译：用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。施主材料外延地沉积在鳍结构的暴露的侧壁上。施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。施主材料被去除，并且从翅片结构形成场效应晶体管。

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