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41. 发明申请

US20120302019A1 NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES 失效
标题翻译： CMOS器件中固体源扩展区非松弛嵌入式压电器
公开(公告)号：US20120302019A1
公开(公告)日：2012-11-29
申请号：US13115314
申请日：2011-05-25
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, JR.
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, JR.
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.
摘要翻译：形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。

42. 发明申请

US20120153397A1 Stressed Fin-FET Devices with Low Contact Resistance 有权
标题翻译：具有低接触电阻的强化Fin-FET器件
公开(公告)号：US20120153397A1
公开(公告)日：2012-06-21
申请号：US13405296
申请日：2012-02-25
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/088
CPC分类号： H01L29/7843 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： An FET device includes a plurality of Fin-FET devices. The fins of the Fin-FET devices are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.
摘要翻译： FET器件包括多个Fin-FET器件。 Fin-FET器件的鳍片由第一材料组成。 FET器件包括第二材料，其外延地融合鳍片。翅片相对于第二材料的上表面垂直凹入。 FET器件还包括形成在鳍片上方和第二材料上的连续硅化物层，以及覆盖该器件的应力衬垫。

43. 发明授权

US08202767B2 Device and method of reducing junction leakage 有权
标题翻译：减少结漏电的装置和方法
公开(公告)号：US08202767B2
公开(公告)日：2012-06-19
申请号：US12789839
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/335
CPC分类号： H01L29/66628 , H01L21/26513 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834
摘要： A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.
摘要翻译：用于减少半导体结中的结漏电的器件和方法包括在器件的源极/漏极区域中形成刻面的凸起结构。掺杂剂从小面凸起结构扩散到小平面凸起结构下面的基底中以形成源极/漏极区域。在刻面凸起结构上施加喷洒注入，以在源/漏区的衬底中产生多深度掺杂物分布。

44. 发明申请

US20120112207A1 METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE 有权
标题翻译：减少超薄氧化物（ETSOI）层的地面沉降的方法
公开(公告)号：US20120112207A1
公开(公告)日：2012-05-10
申请号：US12941771
申请日：2010-11-08
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/762 , H01L29/24
CPC分类号： H01L29/78603 , H01L21/76254
摘要： The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer.
摘要翻译：涉及超薄体BOX和双BOX完全耗尽的SOI器件的本公开内容，以及制造这些器件的方法，其具有外延扩散延迟半导体层，其减缓掺杂剂扩散到SOI沟道中。具有在衬底和SOI沟道之间的外延扩散延迟半导体层的本公开的器件的SOI沟道中的掺杂剂浓度比在没有外延扩散延迟半导体层的器件的SOI沟道中测量的掺杂剂浓度大约小50倍。

45. 发明申请

US20120043610A1 Controlled Fin-Merging for Fin Type FET Devices 有权
标题翻译：鳍型FET器件的受控鳍片合并
公开(公告)号：US20120043610A1
公开(公告)日：2012-02-23
申请号：US12858341
申请日：2010-08-17
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L21/845
摘要： A method for fabricating FET devices is disclosed. The method includes forming continuous fins of a semiconductor material and fabricating gate structures overlaying the continuous fins. After the fabrication of the gate structures, the method uses epitaxial deposition to merge the continuous fins to one another. Next, the continuous fins are cut into segments. The fabricated FET devices are characterized as being non-planar devices. A placement of non-planar FET devices is also disclosed, which includes non- planar devices that have electrodes, and the electrodes contain fins and an epitaxial layer which merges the fins together. The non-planar devices are so placed that their gate structures are in a parallel configuration separated from one another by a first distance, and the fins of differing non-planar devices line up in essentially straight lines. The electrodes of differing FET devices are separated from one another by a cut defined by opposing facets of the electrodes, with the opposing facets also defining the width of the cut. The width of the cut is smaller than one fifth of the first distance which separates the gate structures.
摘要翻译：公开了一种用于制造FET器件的方法。该方法包括形成半导体材料的连续翅片并制造覆盖连续翅片的栅极结构。在门结构的制造之后，该方法使用外延沉积来将连续的翅片彼此合并。接下来，将连续的翅片切成段。所制造的FET器件的特征在于是非平面器件。还公开了非平面FET器件的放置，其包括具有电极的非平面器件，并且电极包含翅片和将翅片合并在一起的外延层。非平面器件被放置成使得它们的栅极结构处于彼此分离第一距离的平行构造，并且不同的非平面器件的鳍以基本上直线排列。不同FET器件的电极通过由电极的相对小面限定的切口彼此分开，相对的面也限定切口的宽度。切口的宽度小于分隔栅极结构的第一距离的五分之一。

46. 发明申请

US20110303915A1 Compressively Stressed FET Device Structures 有权
标题翻译：压缩式FET器件结构
公开(公告)号：US20110303915A1
公开(公告)日：2011-12-15
申请号：US12813311
申请日：2010-06-10
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译：公开了用于制造FET器件结构的方法。所述方法包括接收Si基材料的翅片，以及将鳍片的区域转换为氧化物元件。氧化物元件在制造Fin-FET器件的鳍片上施加压力。施加的压力在Fin-FET器件的器件沟道中引起压应力。所述方法还包括接收Si基材料的矩形构件并将所述构件的区域转换为氧化物元件。所述方法进一步包括在与N个翅片施加压力的同时被N型翅片平行地形成的构件图案化。 Fin-FET器件制造在压缩鳍片中，这导致压缩应力器件通道。还公开了FET器件结构。 FET器件结构具有具有Si基材料的翅片的Fin-FET器件。氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。另外的FET器件结构具有各自具有鳍片的Fin-FET器件。垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

47. 发明授权

US09461169B2 Device and method for fabricating thin semiconductor channel and buried strain memorization layer 有权
标题翻译：用于制造薄半导体沟道和埋层应变记忆层的器件和方法
公开(公告)号：US09461169B2
公开(公告)日：2016-10-04
申请号：US12789792
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/00 , H01L21/84 , H01L29/78 , H01L21/02 , H01L21/265
CPC分类号： H01L29/7847 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L29/7841 , H01L29/785
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.
摘要翻译：用于在半导体层中诱发应力的装置和方法包括提供具有形成在第一半导体层和第二半导体层之间的介电层的衬底，并且处理第二半导体层以形成非晶化材料。应力层沉积在第一半导体层上。将晶片退火以通过使非晶化材料重结晶来在第二半导体层中记忆应力。

48. 发明授权

US08900936B2 FinFET device having reduce capacitance, access resistance, and contact resistance 有权
标题翻译： FinFET器件具有降低电容，访问电阻和接触电阻
公开(公告)号：US08900936B2
公开(公告)日：2014-12-02
申请号：US13017966
申请日：2011-01-31
申请人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
发明人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
IPC分类号： H01L29/772 , H01L21/336 , H01L29/66 , H01L29/417 , H01L29/78
CPC分类号： H01L29/66803 , H01L29/41791 , H01L29/785
摘要： A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each second spacer is adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.
摘要翻译：形成具有减小的电容，存取电阻和接触电阻的鳍状场效应晶体管（finFET）器件。提供掩埋氧化物，鳍状物，栅极和第一间隔物。该鳍被掺杂以形成在栅极下方延伸的延伸结。第二间隔件形成在延伸接头的顶部。每个第二间隔件邻近门的任一侧的第一间隔件之一。延伸结和未被栅极保护的埋入氧化物，第一间隔物和第二间隔物被回蚀刻以产生空隙。空隙填充有半导体材料，使得半导体材料的顶表面延伸到延伸接头的顶表面之下，以形成凹陷的源极 - 漏极区域。在凹陷的源极 - 漏极区域，延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。

49. 发明授权

US08673738B2 Shallow trench isolation structures 有权
标题翻译：浅沟隔离结构
公开(公告)号：US08673738B2
公开(公告)日：2014-03-18
申请号：US13531780
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/76
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
摘要翻译：提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

50. 发明授权

US08617956B2 Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device 有权
公开(公告)号：US08617956B2
公开(公告)日：2013-12-31
申请号：US12859414
申请日：2010-08-19
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/36
CPC分类号： H01L29/0847 , H01L21/28114 , H01L29/165 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/78 , H01L29/7848
摘要： A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

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