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41. 发明申请

US20120326230A1 SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE 审中-公开
标题翻译：绝缘子上的绝缘体与低温下形成隔离的补充金属氧化物半导体
公开(公告)号：US20120326230A1
公开(公告)日：2012-12-27
申请号：US13166714
申请日：2011-06-22
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L27/092 , H01L21/762
CPC分类号： H01L29/0649 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) with an isolation formed at a low temperature and methods for constructing the same. An example method includes infusing an insulation material at a low temperature to form a silicon-based insulator between the active regions.
摘要翻译：具有隔离形成在低温下的绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）及其构造方法。一种示例性方法包括在低温下注入绝缘材料以在活性区域之间形成硅基绝缘体。

42. 发明申请

US20120319232A1 Self-Aligned Dual Depth Isolation and Method of Fabrication 失效
标题翻译：自对准双深度隔离和制作方法
公开(公告)号：US20120319232A1
公开(公告)日：2012-12-20
申请号：US13598992
申请日：2012-08-30
申请人： Kangguo Cheng , Robert Heath Dennard , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Robert Heath Dennard , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L29/06
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/76283 , H01L27/1104
摘要： FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.
摘要翻译：提供了FDSOI器件及其制造方法。一方面，一种制造装置的方法包括以下步骤。提供具有基板，BOX和SOI层的晶片。硬掩模层沉积在SOI层上。光致抗蚀剂层沉积在硬掩模层上并且被图案化成一组片段。执行倾斜的植入物以损坏被片段覆盖或遮蔽的硬掩模层的所有部分。移除由植入物损坏的硬掩模层的部分。通过硬掩模层执行第一蚀刻，以在SOI层，BOX和衬底的至少一部分中形成深沟槽。使用图案化的光致抗蚀剂层对硬掩模层进行图案化。通过硬掩模层进行第二蚀刻，以在SOI层中形成浅沟槽。

43. 发明申请

US20120153397A1 Stressed Fin-FET Devices with Low Contact Resistance 有权
标题翻译：具有低接触电阻的强化Fin-FET器件
公开(公告)号：US20120153397A1
公开(公告)日：2012-06-21
申请号：US13405296
申请日：2012-02-25
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/088
CPC分类号： H01L29/7843 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： An FET device includes a plurality of Fin-FET devices. The fins of the Fin-FET devices are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.
摘要翻译： FET器件包括多个Fin-FET器件。 Fin-FET器件的鳍片由第一材料组成。 FET器件包括第二材料，其外延地融合鳍片。翅片相对于第二材料的上表面垂直凹入。 FET器件还包括形成在鳍片上方和第二材料上的连续硅化物层，以及覆盖该器件的应力衬垫。

44. 发明授权

US08202767B2 Device and method of reducing junction leakage 有权
标题翻译：减少结漏电的装置和方法
公开(公告)号：US08202767B2
公开(公告)日：2012-06-19
申请号：US12789839
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/335
CPC分类号： H01L29/66628 , H01L21/26513 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834
摘要： A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.
摘要翻译：用于减少半导体结中的结漏电的器件和方法包括在器件的源极/漏极区域中形成刻面的凸起结构。掺杂剂从小面凸起结构扩散到小平面凸起结构下面的基底中以形成源极/漏极区域。在刻面凸起结构上施加喷洒注入，以在源/漏区的衬底中产生多深度掺杂物分布。

45. 发明申请

US20120112207A1 METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE 有权
标题翻译：减少超薄氧化物（ETSOI）层的地面沉降的方法
公开(公告)号：US20120112207A1
公开(公告)日：2012-05-10
申请号：US12941771
申请日：2010-11-08
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/762 , H01L29/24
CPC分类号： H01L29/78603 , H01L21/76254
摘要： The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer.
摘要翻译：涉及超薄体BOX和双BOX完全耗尽的SOI器件的本公开内容，以及制造这些器件的方法，其具有外延扩散延迟半导体层，其减缓掺杂剂扩散到SOI沟道中。具有在衬底和SOI沟道之间的外延扩散延迟半导体层的本公开的器件的SOI沟道中的掺杂剂浓度比在没有外延扩散延迟半导体层的器件的SOI沟道中测量的掺杂剂浓度大约小50倍。

46. 发明申请

US20120032267A1 DEVICE AND METHOD FOR UNIFORM STI RECESS 审中-公开
标题翻译：用于均匀STI记录的装置和方法
公开(公告)号：US20120032267A1
公开(公告)日：2012-02-09
申请号：US12851966
申请日：2010-08-06
申请人： KANGGUO CHENG , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： KANGGUO CHENG , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L29/06 , H01L21/302
CPC分类号： H01L21/31111 , H01L21/31155 , H01L21/76237
摘要： A semiconductor device and method for forming the semiconductor device include forming structures in a semiconductor substrate. The structures have two or more different spacings between them. A dielectric material is deposited in the spacings. Ion species are implanted to a depth in the dielectric material to change an etch rate of the dielectric material down to the depth. The dielectric material having the ion species is etched selective to the dielectric material below the depth such that a substantially uniform depth in the dielectric material is created across the at least two spacings.
摘要翻译：用于形成半导体器件的半导体器件和方法包括在半导体衬底中形成结构。这些结构在它们之间具有两个或更多个不同的间隔。电介质材料以间隔沉积。将离子物质注入电介质材料中的深度以将介电材料的蚀刻速率改变到深度。具有离子种类的电介质材料被选择性地蚀刻到深度以下的电介质材料，使得跨越至少两个间隔产生电介质材料中基本均匀的深度。

47. 发明申请

US20110303915A1 Compressively Stressed FET Device Structures 有权
标题翻译：压缩式FET器件结构
公开(公告)号：US20110303915A1
公开(公告)日：2011-12-15
申请号：US12813311
申请日：2010-06-10
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译：公开了用于制造FET器件结构的方法。所述方法包括接收Si基材料的翅片，以及将鳍片的区域转换为氧化物元件。氧化物元件在制造Fin-FET器件的鳍片上施加压力。施加的压力在Fin-FET器件的器件沟道中引起压应力。所述方法还包括接收Si基材料的矩形构件并将所述构件的区域转换为氧化物元件。所述方法进一步包括在与N个翅片施加压力的同时被N型翅片平行地形成的构件图案化。 Fin-FET器件制造在压缩鳍片中，这导致压缩应力器件通道。还公开了FET器件结构。 FET器件结构具有具有Si基材料的翅片的Fin-FET器件。氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。另外的FET器件结构具有各自具有鳍片的Fin-FET器件。垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

48. 发明授权

US09461169B2 Device and method for fabricating thin semiconductor channel and buried strain memorization layer 有权
标题翻译：用于制造薄半导体沟道和埋层应变记忆层的器件和方法
公开(公告)号：US09461169B2
公开(公告)日：2016-10-04
申请号：US12789792
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/00 , H01L21/84 , H01L29/78 , H01L21/02 , H01L21/265
CPC分类号： H01L29/7847 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L29/7841 , H01L29/785
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.
摘要翻译：用于在半导体层中诱发应力的装置和方法包括提供具有形成在第一半导体层和第二半导体层之间的介电层的衬底，并且处理第二半导体层以形成非晶化材料。应力层沉积在第一半导体层上。将晶片退火以通过使非晶化材料重结晶来在第二半导体层中记忆应力。

49. 发明授权

US08552487B2 SOI trench DRAM structure with backside strap 有权
标题翻译：具有背面带的SOI沟槽DRAM结构
公开(公告)号：US08552487B2
公开(公告)日：2013-10-08
申请号：US13568601
申请日：2012-08-07
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： A semiconductor structure includes a SOI substrate having a top silicon layer overlying an insulation layer, which overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, which device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlying the doped portion, the backside strap being coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlying the first portion.
摘要翻译：半导体结构包括：SOI衬底，其具有覆盖在底部硅层上的绝缘层的顶部硅层; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，位于掺杂部分下面的背侧带的至少第一部分，背面带在背面带的第一端处耦合到顶部硅层的掺杂部分，并且连接到电容器在背面带的第二端; 以及第二外延沉积材料，其至少部分地覆盖在顶部硅层的掺杂部分上，第二外延沉积材料进一步至少部分地覆盖在第一部分上。

50. 发明授权

US08343819B2 Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same 有权
标题翻译：具有片上电阻的非常薄的绝缘体上半导体（ETSOI）集成电路及其形成方法
公开(公告)号：US08343819B2
公开(公告)日：2013-01-01
申请号：US12687273
申请日：2010-01-14
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/00
CPC分类号： H01L27/1214 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.
摘要翻译：提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。还提供了形成上述电气装置的方法。

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