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41. 发明授权

US08116122B2 Spin-transfer torque memory self-reference read method 有权
标题翻译：自旋转矩存储器自参考读取方式
公开(公告)号：US08116122B2
公开(公告)日：2012-02-14
申请号：US12147723
申请日：2008-06-27
申请人： Hai Li , Yiran Chen , Hongyue Liu , Kang Yong Kim , Dimitar V. Dimitrov , Henry F. Huang
发明人： Hai Li , Yiran Chen , Hongyue Liu , Kang Yong Kim , Dimitar V. Dimitrov , Henry F. Huang
IPC分类号： G11C11/00
CPC分类号： G11C11/1673 , G11C7/06 , G11C7/065 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5006 , Y10S977/933
摘要： A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.
摘要翻译：描述了自旋转移力矩存储装置和自参考读取方案。读取自旋传递转矩存储单元的一种自参考方法包括：通过磁性隧道结数据单元施加第一读取电流并形成第一位线读取电压，所述磁性隧道结数据单元具有第一电阻状态并存储第一电压存储装置中的第一位线读取电压。然后通过磁性隧道结数据单元施加低电阻状态的极化写入电流，形成低的第二电阻状态磁隧道结数据单元。第二读取电流通过低的第二电阻状态磁隧道结数据单元施加以形成第二位线读取电压。第二位线读取电压被存储在第二电压存储装置中。该方法还包括将第一位线读取电压与第二位线读取电压进行比较，以确定磁性隧道结数据单元的第一电阻状态是高电阻状态还是低电阻状态。

42. 发明授权

US08085606B2 Input-output line sense amplifier having adjustable output drive capability 有权
标题翻译：具有可调输出驱动能力的输入输出线路读出放大器
公开(公告)号：US08085606B2
公开(公告)日：2011-12-27
申请号：US12549200
申请日：2009-08-27
申请人： Kang Yong Kim , Chulmin Jung
发明人： Kang Yong Kim , Chulmin Jung
IPC分类号： G11C11/00 , G11C7/00 , G11C7/02
CPC分类号： G11C7/1096 , G11C7/00 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C11/4091 , G11C11/4097 , G11C13/004 , H03F3/16
摘要： An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.
摘要翻译：输入 - 输出线路读出放大器被配置为通过输入 - 输出信号线将输入数据信号驱动到输出驱动器电路，输入 - 输出线路读出放大器具有输出驱动级，其具有多个不同的可编程输出驱动能力，以定制读出放大器的输出驱动。

43. 发明授权

US08073890B2 Continuous high-frequency event filter 有权
标题翻译：连续高频事件滤波器
公开(公告)号：US08073890B2
公开(公告)日：2011-12-06
申请号：US11360093
申请日：2006-02-22
申请人： Tyler Gomm , Kang Yong Kim
发明人： Tyler Gomm , Kang Yong Kim
IPC分类号： G06F17/10
CPC分类号： H03L7/0814 , G06F7/62 , G11C7/22 , G11C7/222 , H03L7/0805 , H03L7/085 , H03L7/089
摘要： A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.
摘要翻译：一种用于响应于由事件信号表示的N个事件来产生有效输出信号的电路和方法。计数器电路被配置为响应于事件信号递增和递减一系列值。耦合到计数器电路的检测逻辑被配置为检测序列的至少第一和第二值。检测逻辑还被配置为产生有效输出信号并且响应于检测到第一值而切换到检测第二值，并且产生有效输出信号并且响应于检测到第二值而切换到检测第一值。第一个值和第二个值用N个数值分隔。

44. 发明申请

US20110254604A1 Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage 有权
标题翻译：使用线路入口点控制可变延迟线来修改线路电源电压
公开(公告)号：US20110254604A1
公开(公告)日：2011-10-20
申请号：US13171755
申请日：2011-06-29
申请人： Tyler Gomm , Kang Yong Kim , Jongtae Kwak
发明人： Tyler Gomm , Kang Yong Kim , Jongtae Kwak
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.
摘要翻译：本文公开了一种VDL / DLL架构，其中至少将VDL，VccVDL的电源调节为输入信号（ClkIn）入口到VDL中的函数。具体地说，当通过VDL的延迟相对较小（当入口点朝向VDL的右侧（或最小延迟）边缘）时，VccVDL被调节为较高，并且当延迟相对较高时（当入口点朝向VDL的左侧（或最大延迟）边缘）。这提供了在VDL的各个阶段的分级延迟，但是不需要分别设计每个阶段。其他优点包括可在更宽的频率范围内操作的VDL / DLL设计，以及减少的级数，包括减少数量的缓冲级。此外，当使用所公开的技术时，可以完全省去缓冲阶段。另外，所公开的VDL架构可以用于可能有利的是通过作为VDL入口点的函数的可变延迟来延迟信号的任何情况。

45. 发明授权

US08023340B2 Signal transfer apparatus and methods 有权
标题翻译：信号传输装置及方法
公开(公告)号：US08023340B2
公开(公告)日：2011-09-20
申请号：US12730994
申请日：2010-03-24
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G11C7/103 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括被配置为接收多个信号的多个节点。信号可以表示存储在诸如存储器装置的装置的多个存储单元中的信息。该设备可以包括多个传输路径，其具有耦合在节点和输出节点之间的存储元件。传输路径可以被配置为经由传输路径之一将信号的选定信号从节点之一传送到输出节点。传送路径可以被配置为仅将所选信号的值保存在仅一个存储元件中。每个传送路径可以仅包括一个存储元件。公开了包括附加装置，系统和方法的其它实施例。

46. 发明申请

US20090279367A1 POWER SAVING SENSING SCHEME FOR SOLID STATE MEMORY 有权
标题翻译：用于固态存储器的省电感应方案
公开(公告)号：US20090279367A1
公开(公告)日：2009-11-12
申请号：US12502932
申请日：2009-07-14
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C7/10 , G11C7/02
CPC分类号： G11C8/12 , G11C7/103 , G11C8/18
摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.
摘要翻译：公开了诸如涉及固态存储器件的方法和装置。一种这样的方法包括选择存储器阵列中的多个存储器单元。确定存储在所选择的多个存储单元中的多个数据位的状态。在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。顺序提供多个数据位作为输出。在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。

47. 发明授权

US07596039B2 Input-output line sense amplifier having adjustable output drive capability 有权
标题翻译：具有可调输出驱动能力的输入输出线路读出放大器
公开(公告)号：US07596039B2
公开(公告)日：2009-09-29
申请号：US11706937
申请日：2007-02-14
申请人： Kang Yong Kim , Chulmin Jung
发明人： Kang Yong Kim , Chulmin Jung
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/1096 , G11C7/00 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C11/4091 , G11C11/4097 , G11C13/004 , H03F3/16
摘要： An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.
摘要翻译：输入 - 输出线路读出放大器被配置为通过输入 - 输出信号线将输入数据信号驱动到输出驱动器电路，输入 - 输出线路读出放大器具有输出驱动级，其具有多个不同的可编程输出驱动能力，以定制读出放大器的输出驱动。

48. 发明申请

US20090059707A1 POWER SAVING SENSING SCHEME FOR SOLID STATE MEMORY 有权
公开(公告)号：US20090059707A1
公开(公告)日：2009-03-05
申请号：US11847559
申请日：2007-08-30
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C8/12
CPC分类号： G11C8/12 , G11C7/103 , G11C8/18
摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

49. 发明授权

US07382678B2 Delay stage-interweaved analog DLL/PLL 有权
标题翻译：延迟级交织模拟DLL / PLL
公开(公告)号：US07382678B2
公开(公告)日：2008-06-03
申请号：US11297768
申请日：2005-12-08
申请人： Kang Yong Kim , Dong Myung Choi
发明人： Kang Yong Kim , Dong Myung Choi
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0802 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/10
摘要： A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种使得可以根据可能取决于输入参考时钟的频率的操作条件对模拟延迟锁定环（DLL）或锁相环（PLL）的延迟级进行编程的方法。所产生的优化延迟级允许宽的频率范围的操作，在宽的输入时钟频率范围内的快速锁定时间以及在高时钟频率下的较低的电流消耗。通过允许在给定操作期间激活的模拟延迟级的数量被灵活地设置来实现更好的性能。未使用的延迟级的停用或关闭在较高频率下节省功率。通过为各种输入时钟频率使用灵活数量的延迟级来增加操作的高频范围。由于管理摘要的规则，本摘要不应用于解释索赔。

50. 发明授权

US07038511B2 System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits 失效
标题翻译：用于比较和补偿精细延迟与粗略延迟电路之间延迟变化的系统和方法
公开(公告)号：US07038511B2
公开(公告)日：2006-05-02
申请号：US10940187
申请日：2004-09-13
申请人： Kang Yong Kim , Gary Johnson
发明人： Kang Yong Kim , Gary Johnson
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0814 , H03L7/0818 , H03L7/089
摘要： A compensation circuit and method for compensating for variations in time delay adjustments of synchronizing circuits that synchronize an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal. The time delay relationship between fine and coarse delay circuits of an adjustable delay circuit is adjusted to compensate for variations from an expected time delay relationship.
摘要翻译：一种补偿电路和方法，用于补偿同步电路的时间延迟调整的变化，所述同步电路响应于外部时钟信号，将施加到集成电路的外部时钟信号与在集成电路中产生的内部时钟信号同步。调节可调延迟电路的精细和粗略延迟电路之间的时间延迟关系以补偿来自预期时间延迟关系的变化。

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