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41. 发明申请

US20080005479A1 SYSTEMS AND METHODS FOR PROVIDING REMOTE PRE-FETCH BUFFERS 有权
标题翻译：用于提供远程预电效应缓冲器的系统和方法
公开(公告)号：US20080005479A1
公开(公告)日：2008-01-03
申请号：US11419586
申请日：2006-05-22
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1673
摘要： Systems and methods for providing remote pre-fetch buffers. The systems include a computer memory system with a memory controller, one or more memory busses connected to the memory controller, and at least one memory subsystem in communication with the memory controller via the memory busses. The memory controller generates, receives and responds to memory access requests including unsolicited data transfers. The memory subsystem includes one or more memory devices and logic to initiate an unsolicited data transfer to the memory controller based on analysis performed at the memory subsystem of prior memory access requests received by the memory subsystem.
摘要翻译：用于提供远程预取缓冲区的系统和方法。这些系统包括具有存储器控制器的计算机存储器系统，连接到存储器控制器的一个或多个存储器总线以及经由存储器总线与存储器控制器通信的至少一个存储器子系统。存储器控制器生成，接收并响应包括主动请求的数据传输的存储器访问请求。存储器子系统包括一个或多个存储器设备和逻辑，用于基于在存储器子系统处对由存储器子系统接收的先前存储器访问请求执行的分析来发起向存储器控制器的非请求数据传输。

42. 发明申请

US20070297397A1 Memory Systems for Automated Computing Machinery 失效
标题翻译：自动计算机存储系统
公开(公告)号：US20070297397A1
公开(公告)日：2007-12-27
申请号：US11426047
申请日：2006-06-23
申请人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
IPC分类号： H04L12/50
CPC分类号： G06F13/1684 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module, where memory module includes a memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, with the high speed memory bus connected to the memory hub device by a negligible electrical stub.
摘要翻译：公开了包括存储器控制器的存储器系统; 一个内存总线终端; 连接存储器控制器，存储器总线终端器和至少一个存储器模块的高速存储器总线，其中存储器模块包括存储器集线器设备，由存储器集线器设备服务的高速随机存取存储器，两个总线信号端口和在存储器模块上制造的高速存储器总线的一段，以便将总线信号端口和存储器集线器设备互连，高速存储器总线通过可忽略的电接头连接到存储器集线器装置。

43. 发明授权

US06775751B2 System and method for using a compressed main memory based on degree of compressibility 失效
公开(公告)号：US06775751B2
公开(公告)日：2004-08-10
申请号：US10213840
申请日：2002-08-06
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F1300
CPC分类号： G06F12/023 , G06F12/08 , G06F12/127 , G06F2212/401
摘要： A method and structure for reducing access latency and contention in a processing system is disclosed. The invention detects when the amount of available memory is outside a prescribed range, and responsively selects data blocks for compression (to add to the available memory,) or decompression (to use surplus available memory for uncompressed data,) until the amount of available memory is within the prescribed range. When data blocks are compressed, a DOC is determined and stored as an attribute in the directory entry associated with the data block. A most recently used list of recent data block addresses prevents those, as well those data blocks with poor DOC attributes, from being selected for recompression. All zero data blocks are detected to avoid standard compression/decompression overhead.

44. 发明授权

US06446145B1 Computer memory compression abort and bypass mechanism when cache write back buffer is full 失效
标题翻译：当缓存回写缓冲区已满时，计算机内存压缩中止和旁路机制
公开(公告)号：US06446145B1
公开(公告)日：2002-09-03
申请号：US09478556
申请日：2000-01-06
申请人： David Har , Charles O. Schulz , Robert B. Tremaine
发明人： David Har , Charles O. Schulz , Robert B. Tremaine
IPC分类号： G06F1300
CPC分类号： G06F12/08 , G06F12/0804 , G06F2212/401
摘要： In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies, a method and apparatus for enabling termination of a pending compression operation for the purpose of writing the data directly to the main memory, bypassing the compressor hardware during stall conditions. Memory space (compressibility) is sacrificed for higher system performance during these temporary write back stall events. A background memory scrub later detects and recovers the “lost” compressibility by recycling the uncompressed data back through the compressor during idle periods.
摘要翻译：在具有主存储器的处理系统中，其中以压缩格式存储信息以便通过压缩效率获得额外的存储的方法和装置，用于终止待处理的压缩操作以将数据直接写入主要的方法和装置存储器，在失速条件下绕过压缩机硬件。在这些临时回写失速事件期间，为了提高系统性能，牺牲了内存空间（可压缩性）。后台存储器擦除后来通过在空闲期间将压缩后的数据再循环通过压缩器来检测并恢复“丢失”可压缩性。

45. 发明申请

US20130262791A1 HOST-SIDE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS 审中-公开
标题翻译：内存系统动态更改频率的主机支持
公开(公告)号：US20130262791A1
公开(公告)日：2013-10-03
申请号：US13430807
申请日：2012-03-27
申请人： Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
发明人： Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： G06F12/00
CPC分类号： G11C29/023 , G06F1/324 , G06F1/3275 , G06F13/1689 , G11C29/028 , Y02D10/126 , Y02D10/14
摘要： An embodiment is a method for operating a memory system, the method including storing initial calibration values for each of a first frequency and second frequency for a memory device, performing a periodic calibration to determine a calibration update value for operation of the memory device at the first frequency, combining the calibration update value with the initial calibration value for the first frequency to provide an updated calibration for operation of the memory device at an operating frequency of the first frequency and receiving a frequency change request at a memory controller associated with the memory device. The method further includes blocking traffic to the memory device, adjusting operating frequency to the second frequency while the memory device remains powered, combining the calibration update value with the initial calibration value for the second frequency for operation at the second frequency and enabling traffic to the memory device.
摘要翻译：一个实施例是用于操作存储器系统的方法，该方法包括存储用于存储器件的第一频率和第二频率中的每一个的初始校准值，执行周期性校准以确定用于在存储器装置的操作的校准更新值将所述校准更新值与所述第一频率的初始校准值组合，以提供用于在所述第一频率的操作频率下操作所述存储器件的更新校准，并且在与所述存储器相关联的存储器控制器处接收频率改变请求设备。该方法还包括阻止对存储器件的流量，在存储器件保持通电的同时将操作频率调整到第二频率，将校准更新值与用于第二频率的第二频率的初始校准值相组合，并使流量达到存储设备。

46. 发明授权

US08516409B2 Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device 有权
标题翻译：实现垂直管芯堆叠，在多晶硅通孔堆叠半导体器件中分配多个管芯的逻辑功能
公开(公告)号：US08516409B2
公开(公告)日：2013-08-20
申请号：US12944020
申请日：2010-11-11
申请人： Paul W. Coteus , Kyu-Hyoun Kim , Robert B. Tremaine
发明人： Paul W. Coteus , Kyu-Hyoun Kim , Robert B. Tremaine
IPC分类号： G06F17/50
CPC分类号： H01L25/0657 , G11C5/04 , G11C17/143 , G11C17/16 , G11C29/12 , G11C29/785 , G11C29/802 , G11C2229/763 , G11C2229/766 , H01L23/481 , H01L25/18 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565
摘要： A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a respective predefined function. The respective predefined function is executed in each respective die and a respective functional result is provided to an adjacent die in the die stack. Each die in the die stack includes logic for providing die identification. An operational die signature is formed by combining a plurality of selected signals on each die. A die signature is coupled to a next level adjacent die using TSV interconnections where it is combined with that die signature.
摘要翻译：一种用于实现芯片堆叠以在多个裸片上分布逻辑功能的方法和电路，以及提供了通过硅片通过堆叠的半导体器件的裸片识别和备用，以及设置有被摄体电路的设计结构。管芯堆叠中的每个管芯包括用于实现相应的预定义功能的预定义功能逻辑。在每个相应的管芯中执行相应的预定义功能，并且将相应的功能结果提供给管芯堆叠中的相邻管芯。管芯堆叠中的每个管芯包括用于提供管芯识别的逻辑。通过组合每个管芯上的多个选择的信号来形成操作管芯签名。使用TSV互连将芯片签名耦合到下一级相邻裸片，其中它与该芯片签名组合。

47. 发明授权

US08493089B2 Programmable logic circuit using three-dimensional stacking techniques 失效
标题翻译：可编程逻辑电路采用三维堆叠技术
公开(公告)号：US08493089B2
公开(公告)日：2013-07-23
申请号：US13080994
申请日：2011-04-06
申请人： Edgar R. Cordero , Robert B. Tremaine
发明人： Edgar R. Cordero , Robert B. Tremaine
IPC分类号： H01L25/00
CPC分类号： H03K19/08 , G11C29/08 , H03K19/17752 , H03K19/17796
摘要： A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal.
摘要翻译：一种可配置的管芯堆叠装置，其包括位于第一衬底上的第一可配置集成电路管芯。第一可配置集成电路管芯包括第一阵列和第一配置存储器管理电路，其包括与第一阵列的接口。第一阵列包括第一逻辑元件和第一配置存储器。可配置管芯堆叠装置还包括位于与第一衬底不同的第二衬底上的第二可配置集成电路管芯。第二可配置集成电路管芯包括第二阵列和第二配置存储器管理电路，其包括到第二阵列的接口。第二阵列包括第二逻辑元件和第二配置存储器。信号耦合到第一配置管理电路和第二配置管理电路，并且第一配置存储器管理电路包括用于控制信号的电路。

48. 发明授权

US08284621B2 Strobe offset in bidirectional memory strobe configurations 有权
标题翻译：双向内存选通配置中的频闪偏移
公开(公告)号：US08284621B2
公开(公告)日：2012-10-09
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C8/18
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译：一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

49. 发明申请

US20120198143A1 Memory Package Utilizing At Least Two Types of Memories 有权
标题翻译：记忆包利用至少两种类型的记忆
公开(公告)号：US20120198143A1
公开(公告)日：2012-08-02
申请号：US13438594
申请日：2012-04-03
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/06
CPC分类号： G06F12/0638 , Y10S707/99931
摘要： A memory package and methods for writing data to and reading data from the memory package are presented. The memory package includes a volatile memory and a high-density memory. Data is written to the memory package at a bandwidth and latency associated with the volatile memory. A directory map associates a volatile memory address with data in the high-density memory. A copy of the directory map is stored in the high-density memory. The methods allow writing to and reading from the memory package using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).
摘要翻译：介绍了一种用于将数据写入数据并从存储器包中读取数据的存储器包和方法。存储器包包括易失性存储器和高密度存储器。数据以与易失性存储器相关联的带宽和延迟写入存储器包。目录图将易失性存储器地址与高密度存储器中的数据相关联。目录图的副本存储在高密度存储器中。该方法允许使用第一存储器读/写接口（例如，DRAM接口等）从存储器包写入和读取，尽管数据存储在不同存储器类型（例如FLASH等）的设备中。

50. 发明授权

US08219746B2 Memory package utilizing at least two types of memories 有权
标题翻译：使用至少两种类型的存储器的存储器封装
公开(公告)号：US08219746B2
公开(公告)日：2012-07-10
申请号：US12576028
申请日：2009-10-08
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F12/0638 , Y10S707/99931
摘要： A memory system and methods for memory manage are presented. The memory system includes a volatile memory electrically connected to a high-density memory; a memory controller that expects data to be written or read to or from the memory system at a bandwidth and a latency associated with the volatile memory; a directory within the volatile memory that associates a volatile memory address with data stored in the high-density memory; and redundant storage in the high-density memory that stores a copy of the association between the volatile memory address and the data stored in the high-density memory. The methods for memory management allow writing to and reading from the memory system using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).
摘要翻译：介绍了一种存储器系统和存储器管理方法。存储器系统包括电连接到高密度存储器的易失性存储器; 期望以与易失性存储器相关联的带宽和等待时间从存储器系统写入或读取数据的存储器控制器; 易失性存储器内的目录，其将易失性存储器地址与存储在高密度存储器中的数据相关联; 以及高密度存储器中的冗余存储器，其存储易失性存储器地址和存储在高密度存储器中的数据之间的关联的副本。用于存储器管理的方法允许使用第一存储器读/写接口（例如DRAM接口等）从存储器系统进行写入和读取，尽管数据存储在不同存储器类型（例如FLASH等）的器件中，。

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