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    • 41. 发明专利
    • PREPARATION OF PHOTOELECTRIC CONVERSION ELEMENT
    • JPS57103371A
    • 1982-06-26
    • JP8030581
    • 1981-05-27
    • KOGYO GIJUTSUIN
    • HAYASHI YUTAKAYAMANAKA MITSUYUKI
    • H01L31/04H01L31/072H01L31/074H01L31/10H01L31/18
    • PURPOSE:To improve the photoelectric conversion efficiency of a solar cell and the like by growing sequentially an SnO2 film wherein recombination levels of minority carriers are increased and a low-resistance SnO2 film on an Si substrate in an oxidizing ambience containing Sn vapor or the like. CONSTITUTION:On an N type Si substrate or a thin Si film formed on another substrate is formed the SnO2 film in the oxidizing ambience containing Sn vapor or Sn compound vapor, whereby the photoelectric conversion element formed of heterojunction is prepared. As this SnO2 film, two layers thereof having different properties are grown. The first-layer SnO2 film is formed to be 10Angstrom or more thick at the temperature in the range of 320 deg.C or less and the recombination levels in the film are increased to raise open-circuit voltage Voc. As for the second-layer SnO2 film formed subsequently, the temperature for growing is raised to 340-420 deg.C, while N type impurity is applied to an ambience as occasion calls to make the film be of low resistance, so as for the high terminal voltage of 0.8 to be obtained at the time of outputting. By this constitution, the conversion efficiency can be improved and thus the device can be made fitted for the solar cell and the like.
    • 42. 发明专利
    • MIS FIELD-EFFECT TRANSISTOR
    • JPS5718364A
    • 1982-01-30
    • JP9352180
    • 1980-07-09
    • KOGYO GIJUTSUIN
    • SEKIKAWA TOSHIHIROHAYASHI YUTAKA
    • H01L27/00H01L21/02H01L21/331H01L27/12H01L29/73H01L29/78H01L29/786
    • PURPOSE:To enable to prevent a short-channel effect and to obtain a highly efficient integrated circuit by a method wherein a low resistive region, to be used for the shielding of a channel region, is provided below the channel region when an IGFET is formed on the substrate consisting of an insulating material or a semi-insulating material. CONSTITUTION:A source and a drain regions 3 and 4 are formed in the thin semiconductor film which was formed on the substrate consisting of an insulating material such as sapphire and the like or a semi-insulating material, and the IGFET is formed by providing a gate electrode 6 on a channel region 2 which is separating the regions 3 and 4 through the intermediary of a gate insulating film 5. At that time, a low resistive region 10 to be used for shielding of the channel region is provided under the region 2 through the intermediary of an insulating film 8. Through these procedures, as the drain field can be shielded in such manner that the channel region 2 is sandwitched in between a gate electrode 6 and the region 10, the short- channel effect is prevented and a highly efficient integrated circuit can be obtained.
    • 44. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPS56105671A
    • 1981-08-22
    • JP905680
    • 1980-01-29
    • KOGYO GIJUTSUIN
    • HAYASHI YUTAKA
    • H01L27/12H01L21/74H01L29/41
    • PURPOSE:To avoid through hole to a substrate by a method wherein when a semiconductor thin film of diamond lattice type or zinc-blende type crystal and other semiconductor thin films are layer-built to form a junction on an insulated substrate, and an electrode take-out region is formed on the thin film on the lower side, a degeneration region is kept formed on the lower thin film. CONSTITUTION:When the lower P type Si thin film 10 is formed on the insualated substrate 1, a crystallized surface is chosen to a (100) face or (110) face larger in an etching speed and an impurity density of a region 10a touching to the substrate 1 is increased as 10 -10 pcs/cm to keep the region 10a in the degeneration state. Then, after an N type Si layer 11 is formed to cause a P-N junction to be constructed between the layer 11 and layer 10, the lower layer 10 is formed with an etching mask layer 12 for forming an external connecting terminal 13 and a hydrazine liquid is injected into an opening formed in the layer 12 to apply an etching to the layer 10. In such a way, since the etching velosity in the degeneration region 10a is less than 1/10 of that of the upper semiconductor thin film, the region 10a cannot be thrusted through if the etching is stopped at the abovesaid region 10.
    • 45. 发明专利
    • MANUFACTURE OF MINUTE STRUCTURE
    • JPS5635421A
    • 1981-04-08
    • JP8427780
    • 1980-06-21
    • KOGYO GIJUTSUIN
    • HAYASHI YUTAKA
    • H01L21/027H01L21/30H01L21/302H01L21/306H01L21/3065
    • PURPOSE:To manufacture a device of good high-frequency properties, by coating an SiO2 film and an Si3N4 film on a semiconductor substrate of one electroconductive type, making openings in these films to produce regions of another electroconductive type in the substrate by diffusion, etching the side faces of the remaining film and producing another region of the former electroconductive type at an etched portion of the film by diffusion so that the latter region is in contact with one of the former regions. CONSTITUTION:A thick SiO2 film 2 is coated on a semiconductor substrate 1 of one electroconductive type and then covered with a thin Si3N4 film 3 and a thin SiO2 film 4. Openings 5, 6 are provided in the films to correspond to diffused regions. The regions 10, 11 of another electroconductive type are produced by diffusion in the portions of the substrate 1 exposed in the openings 5, 6. Thin SiO2 films 101, 111 produced on the regions 10, 11 due to the diffusion are etched off. At the same time, the side faces of the film 2 are etched. Another region 17 of the former electroconductive type is produced by diffusion in the substrate 1 at an etched side face 12 so that a shallow region 17 being diffusion formed is in contact with the former region 10. Other openings 10c, 11c are provided in an SiO2 film 13 being produced as a result of said process, while electrodes 10E, 11C are fitted thereon respectively. Another electrode 1E is coated on the reverse side of the substrate 1.
    • 46. 发明专利
    • INTEGRATED CIRCUIT
    • JPS5490979A
    • 1979-07-19
    • JP15204578
    • 1978-12-11
    • KOGYO GIJUTSUIN
    • HAYASHI YUTAKATARUI YASUO
    • H01L21/8236H01L27/088H01L29/423H01L29/43H01L29/49H01L29/78
    • PURPOSE:To make suitable the IC the massproduction, by forming the transistor region of enhancement and depletion type, and by selecting the type of transistor as required, or forming the both at the same time. CONSTITUTION:The SiO2 film 2 is coated on the N type Si substrate 1, the region forming the enhancement transistor 3 and depletion type transistor 4 is removed, and the thin SiO2 film is produced on it. Next, the SiO2 film corresponding to the source, drain and cross under region is removed, and the P type polycrystal Si layer 4 and the SiO2 film 5 are grown on the entire surface. After that, the polycrystal layers 532 and 542 being the gate of two transistors are made independent with photo etching, and the P type source and drain regions 931, 941, 933 and 943 are formed in the substrate 1 at the both sides by diffusion. Next, the SiO2 film 7 is coated on the entire surface, opening is provided, and the electrode 832 when the enhancement type is desired to obtain, and the electrode 842 when the depletion type is desired, are respectively selected.
    • 47. 发明专利
    • SEMICONDUCTOR DEVICE AND ITS USAGE
    • JPS5458378A
    • 1979-05-11
    • JP12448577
    • 1977-10-19
    • KOGYO GIJUTSUIN
    • SUZUKI HIDEKAZUHAYASHI YUTAKANAGAI KIYOKO
    • H01L29/88H01L21/8247H01L29/788H01L29/792
    • PURPOSE:To establish the device having high speed switching and oscillating action, by enabling the circuit integration through the organic combination of FET and tunnel diode. CONSTITUTION:On the p type substrate 1, the shrinked n soarce layer 2, drain layer 3, and shrinked r layer 4 are placed, forming the tunnel junction 8 between the layers 3, 4, and 2. Next, the V groove is etched and the gate electrode 6 is made on the surface via the insulation film 5. To the layers 2 and 3, the electrodes S D in contact with the layer 7 and the tunnel junction operation bias electrodes B1 and B2 are made to the layer 4. The junction 8 shows dynatron type negative resistance due to tunnel effect. When the bias of the layer 4 is fixed to a, the channel resistance of FET considering as load is changed with the voltage applied to the gate 6, and as the channel approaches ON, the load line is risen and the output is picked up as the voltage e, f opposed to the condition cd from the layer 3. In this case, the switching is not required for power application to the channel because of the tunnel effect, then very high speed switching can be made.
    • 48. 发明专利
    • SEMICONDUCTOR MEMORY UNIT AND ITS WRITING METHOD
    • JPS5458376A
    • 1979-05-11
    • JP12448477
    • 1977-10-19
    • KOGYO GIJUTSUIN
    • HAYASHI YUTAKASUZUKI HIDEKAZUNAGAI KIYOKO
    • G11C17/00G11C16/04H01L21/8247H01L29/417H01L29/788H01L29/792
    • PURPOSE:To prevent earlier deficiency of insulation film and to increase the number of rewriting, by providing the auxiliary region for charge supply in contact with at least a part or one of one of the source and drain. CONSTITUTION:The SiO2 4 and Si3N4 5 are laminated by bridging the p type source and drain 2 and 3 on the n type substrate 1, and the gate electrode 7 is provided. At the boundary of the films 4 and 5 or a part of the film 5, charges are stored and held 6 and memorized. The layers 2 and 3 are provided with the n type auxiliary region 10 and charges are supplied. The region 10 is present under the gate and the end of the region 10 is present in the depletion layer 11 formed by the layers 2 and 3. In writing in, the layers 2 and 3 are back biased to the substrate 1, spreading the depletion layer under the charge holding means 6 and keeping the layer 10 at the same polarity and same potential as the back bias. The gate 7 is held at the potential close to the substrate 1. Thus, the n type carrier is induced with the different potential from the substrate region on the depletion layer of the substrate surface and the n type carrier is injected to the holding means 6. Accordingly, the bias can be less than the avalanche breakdown, no current concentration is caused and the insulation film is not deteriorated.