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41. 发明申请

US20070120218A1 CMOS compatible shallow-trench efuse structure and method 失效
标题翻译： CMOS兼容浅沟槽结构和方法
公开(公告)号：US20070120218A1
公开(公告)日：2007-05-31
申请号：US11290890
申请日：2005-11-30
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L21/268 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.
摘要翻译：提供了包括位于半导体衬底（主体或绝缘体中半导体）的沟槽内的至少一个电子熔丝的半导体结构。根据本发明，电熔丝与位于半导体衬底内的掺杂区电接触。本发明还提供一种制造这种半导体结构的方法，其中嵌入式电熔丝基本上与沟槽隔离区域同时形成。

42. 发明申请

US20070096259A1 Fabrication of bipolar transistor having reduced collector-base capacitance 失效
标题翻译：具有减小的集电极 - 基极电容的双极晶体管的制造
公开(公告)号：US20070096259A1
公开(公告)日：2007-05-03
申请号：US11633380
申请日：2006-12-04
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： A method is provided for fabricating a bipolar transistor in which a collector layer is formed which includes an active portion having a relatively high dopant concentration and a second portion which has a lower dopant concentration. An epitaxial intrinsic base layer is formed to overlie the collector layer in conductive communication with the active portion of the collector layer. A low-capacitance region is formed laterally adjacent to the second portion of the collector layer, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer. An emitter layer is formed to overlie the intrinsic base layer.
摘要翻译：提供一种用于制造双极晶体管的方法，其中形成集电极层，其包括具有较高掺杂剂浓度的有源部分和具有较低掺杂剂浓度的第二部分。外延本征基极层形成为覆盖集电极层，与集电极层的有源部分导电连通。低电容区域形成为与集电极层的第二部分横向相邻，低电容区域包括设置在直接位于本征基极层下方的底切处的电介质区域。形成发射极层以覆盖本征基极层。

43. 发明申请

US20070029576A1 PROGRAMMABLE SEMICONDUCTOR DEVICE CONTAINING A VERTICALLY NOTCHED FUSIBLE LINK REGION AND METHODS OF MAKING AND USING SAME 审中-公开
标题翻译：包含垂直可编程可熔连接区域的可编程半导体器件及其制造和使用方法
公开(公告)号：US20070029576A1
公开(公告)日：2007-02-08
申请号：US11161439
申请日：2005-08-03
申请人： Edward Nowak , Jed Rankin , William Tonti
发明人： Edward Nowak , Jed Rankin , William Tonti
IPC分类号： H01L27/10
CPC分类号： H01L27/10 , H01L23/5256 , H01L29/66795 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a programmable semiconductor device, preferably a FinFET or tri-gate structure, that contains a first contact element, a second contact element, and at least one fin-shaped fusible link region coupled between the first and second contact elements. The second contact element is laterally spaced apart from the first contact element, and the fin-shaped fusible link region has a vertically notched section. A programming current flowing through the fin-shaped fusible link region causes either significant resistance increase or formation of an electric discontinuity in the vertically notched section. Alternatively, the vertically notched section may contain a dielectric material, and application of a programming voltage between a gate electrode overlaying the vertically notched section and one of the contact elements breaks down the dielectric material and allows current flow between the gate electrode and the fin-shaped fusible link region.
摘要翻译：本发明涉及一种可编程半导体器件，优选地为FinFET或三栅极结构，其包含第一接触元件，第二接触元件以及耦合在第一和第二接触元件之间的至少一个鳍状可熔连接区域。第二接触元件与第一接触元件横向间隔开，并且鳍状可熔连接区域具有垂直切口部分。流过翅片状易熔连接区域的编程电流导致垂直切口部分中显着的电阻增加或电中断的形成。或者，垂直切口部分可以包含电介质材料，并且在覆盖垂直切口部分的栅极电极和其中一个接触元件之间施加编程电压会破坏电介质材料，并允许电流在栅电极和鳍片间电流之间流动，形易熔连接区域。

44. 发明申请

US20070026579A1 DOPED SINGLE CRYSTAL SILICON SILICIDED EFUSE 有权
标题翻译：单晶硅晶硅胶
公开(公告)号：US20070026579A1
公开(公告)日：2007-02-01
申请号：US11161320
申请日：2005-07-29
申请人： Edward Nowak , Jed Rankin , William Tonti , Richard Williams
发明人： Edward Nowak , Jed Rankin , William Tonti , Richard Williams
IPC分类号： H01L21/84
CPC分类号： H01L27/10 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.
摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。将单晶硅层图案化成条带。在构图之前或之后，单晶硅层掺杂有一种或多种杂质。至少单晶硅层的上部然后被硅化以形成硅化带。在一个实施例中，整个单晶硅带被硅化以产生硅化物条。在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。上覆的硅化物材料允许熔丝作为未编程状态的导体。然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

45. 发明申请

US20070013001A1 Epitaxial imprinting 失效
标题翻译：外延印记
公开(公告)号：US20070013001A1
公开(公告)日：2007-01-18
申请号：US11182381
申请日：2005-07-15
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L27/12 , H01L27/01
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/84 , H01L27/1203
摘要： The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.
摘要翻译：本发明提供一种用于制造包括底部半导体层的混合衬底的外延压印工艺; 存在于所述底部半导体层顶部的连续掩埋绝缘层; 以及存在于所述连续掩埋绝缘层上的顶部半导体层，其中所述顶部半导体层包括具有不同晶体取向的分离的平面半导体区域，所述分开的平面半导体区域彼此隔离。利用外延生长，晶片接合和再结晶退火的本发明的外延印刷方法。

46. 发明申请

US20060234428A1 METHODS OF IMPLEMENTING AND ENHANCED SILICON-ON-INSULATOR (SOI) BOX STRUCTURES 失效
标题翻译：实施和增强硅绝缘体（SOI）盒结构的方法
公开(公告)号：US20060234428A1
公开(公告)日：2006-10-19
申请号：US11106004
申请日：2005-04-14
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/66772 , H01L21/84 , H01L23/5252 , H01L27/1203 , H01L2924/0002 , Y10S438/928 , H01L2924/00
摘要： Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.
摘要翻译：提供了增强的绝缘体上硅（SOI）掩埋氧化物（BOX）结构和方法来实现增强的SOI BOX结构。将氧注入步骤从背面进行到薄化的硅衬底层。退火步骤从硅衬底层中的氧注入形成厚的掩埋氧化物（BOX）区域。氧注入步骤在氧植入物附近形成隔离区域。背侧注入步骤选择性地掺杂用于形成包括所选择的抗熔丝（AF）器件的SOI器件的SOI器件的隔离区域以及包括PFET和NFET器件的SOI晶体管的隔离区域。

47. 发明申请

US20050275054A1 Autonomic thermal monitor and controller for thin film devices 失效
标题翻译：用于薄膜器件的自动热监测器和控制器
公开(公告)号：US20050275054A1
公开(公告)日：2005-12-15
申请号：US10853800
申请日：2004-05-25
申请人： Zachary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
发明人： Zachary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
IPC分类号： G01K7/01 , H01L27/02 , H01L29/66 , H01L31/0392
CPC分类号： H01L27/0248 , G01K7/01 , H01L29/66992
摘要： A thermal monitor diode is provided that comprises a silicon thin film on an insulator mounted on a silicon substrate. An opening extends through the silicon thin film and through the insulator and partially into the silicon substrate and terminates at an end wall. A conductive material is disposed in the opening and extends to the end wall. The substrate has a P/N junction formed therein adjacent the end wall, and an insulating spacer material surrounds the conductive material and is sufficiently thin to allow temperature excursions in the silicon thin film to pass therethrough. The invention also contemplates a method of forming the diode.
摘要翻译：提供一种热监测二极管，其包括安装在硅衬底上的绝缘体上的硅薄膜。开口延伸穿过硅薄膜并穿过绝缘体并部分地延伸到硅衬底中并终止于端壁。导电材料设置在开口中并延伸到端壁。衬底具有邻近端壁形成的P / N结，并且绝缘间隔物材料围绕导电材料并且足够薄以允许硅薄膜中的温度偏移通过。本发明还考虑了形成二极管的方法。

48. 发明申请

US20050199966A1 Dual work function semiconductor structure with borderless contact and method of fabricating the same 失效
标题翻译：具有无边界接触的双功能半导体结构及其制造方法
公开(公告)号：US20050199966A1
公开(公告)日：2005-09-15
申请号：US11098103
申请日：2005-04-04
申请人： Qiuyi Ye , William Tonti , Yujun Li
发明人： Qiuyi Ye , William Tonti , Yujun Li
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/088 , H01L27/092 , H01L27/108 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10894
摘要： A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.
摘要翻译：提出了一种具有无边界接触的双功能半导体结构及其制造方法。该结构可以包括具有基本无帽栅极的场效应晶体管（FET）和与无盖栅极相邻的扩散部的导电接触，其中导电触点与栅极无边界。由于该结构是双重功能结构，所以允许导电接触件在无盖栅极上延伸而不与其电连接。

49. 发明授权

US08575718B2 Programmable electrical fuse 失效
标题翻译：可编程电气保险丝
公开(公告)号：US08575718B2
公开(公告)日：2013-11-05
申请号：US13289529
申请日：2011-11-04
申请人： Michael J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michael J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/52 , H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

50. 发明申请

US20120280356A1 UNIFORMLY ALIGNED WELL AND ISOLATION REGIONS IN A SUBSTRATE AND RESULTING STRUCTURE 审中-公开
标题翻译：在基板和结构结构中均匀分布的井和隔离区
公开(公告)号：US20120280356A1
公开(公告)日：2012-11-08
申请号：US13552695
申请日：2012-07-19
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William Tonti
IPC分类号： H01L29/06
CPC分类号： H01L21/76232
摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
摘要翻译：本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。距离对于每个沟槽和每个相邻的隔离区域是成比例的。

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