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41. 发明授权

US4755478A Method of forming metal-strapped polysilicon gate electrode for FET device 失效
标题翻译：形成用于FET器件的金属带状多晶硅栅电极的方法
公开(公告)号：US4755478A
公开(公告)日：1988-07-05
申请号：US84719
申请日：1987-08-13
申请人： John R. Abernathey , John E. Cronin , Jerome B. Lasky
发明人： John R. Abernathey , John E. Cronin , Jerome B. Lasky
IPC分类号： H01L29/78 , H01L21/225 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L23/52 , H01L21/425
CPC分类号： H01L29/66575 , H01L21/2257 , H01L21/28061 , H01L29/41783 , H01L29/66545
摘要： A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer. First and second diffusion having first and second silicide electrodes are then formed on the substrate, to provide low sheet resistance source and drain electrodes. An insulating layer is then formed on the substrate, and is planarized to expose an upper surface of the gate mask. The gate mask is then removed in wet H.sub.3 PO.sub.4 to define an aperture in the insulating layer that exposes the polysilicon layer, and a conductive material is selectively grown on the substrate to provide a metal-strapped polysilicon gate electrode that is relatively co-planar with the planarized insulating layer.

42. 发明授权

US07797241B2 Global information network product publication system 有权
标题翻译：全球信息网络产品出版系统
公开(公告)号：US07797241B2
公开(公告)日：2010-09-14
申请号：US09931492
申请日：2001-08-16
申请人： Thomas J. Colson , John E. Cronin , Samuel C. Baxter , Robert Cantrell
发明人： Thomas J. Colson , John E. Cronin , Samuel C. Baxter , Robert Cantrell
IPC分类号： G06F17/30
CPC分类号： G06Q10/10
摘要： A system and a method of publishing an product document for clients for the purpose of publicly disclosing an invention to end users on the Global Information Network. The system includes a first Web site system having a publicly accessible database for storing a plurality of product documents received from clients. The Web site also includes a search engine accessible to the end user. The search engine is in electronic communication with the database and can receive a search request the end user, allowing the end user access to one or more of the product documents. The product document preferably includes a primary text file and attachment files which may include drawing files. The product documents may be digitally notarized and time/date stamped.
摘要翻译：为客户公开产品文档的系统和方法，以向全球信息网络上的最终用户公开发明。该系统包括具有用于存储从客户端接收的多个产品文档的可公开访问的数据库的第一网站系统。该网站还包括最终用户可访问的搜索引擎。搜索引擎与数据库进行电子通信，并可以接收最终用户的搜索请求，允许最终用户访问一个或多个产品文档。产品文档优选地包括主文本文件和可以包括绘图文件的附件文件。产品文件可能经过数字公证，时间/日期盖印。

43. 发明授权

US06753498B2 Automated electrode replacement apparatus for a plasma processing system 失效
标题翻译：用于等离子体处理系统的自动电极更换装置
公开(公告)号：US06753498B2
公开(公告)日：2004-06-22
申请号：US10346186
申请日：2003-01-17
申请人： Murray D. Sirkis , Eric Strang , Yu Wang Bibby , John E. Cronin
发明人： Murray D. Sirkis , Eric Strang , Yu Wang Bibby , John E. Cronin
IPC分类号： B23K1000
CPC分类号： H01J37/32009 , H01J37/32605
摘要： A plasma processing system includes an automated electrode retention mechanism (130) for providing automated engagement of a source electrode (152) with a drive electrode (154). In addition, an automated electrode handling system (320) is provided that has the ability to remove a source electrode (152) from the electrode retention mechanism and replace it with a second source electrode (152′) that is stored in a staging area (340) outside the plasma processing system vacuum chamber. The system may operate automatically under program control of a computer system (200) coupled thereto.
摘要翻译：等离子体处理系统包括用于提供源电极（152）与驱动电极（154）的自动接合的自动电极保持机构（130）。另外，提供了自动电极处理系统（320），其具有从电极固定机构移除源电极（152）并将其替换为存储在分段区域中的第二源电极（152'） 340）等离子体处理系统真空室外。系统可以在与其耦合的计算机系统（200）的程序控制下自动操作。

44. 发明授权

US06715246B1 Ceiling tile transmitter and receiver system 失效
标题翻译：天花板发射机和接收机系统
公开(公告)号：US06715246B1
公开(公告)日：2004-04-06
申请号：US09604523
申请日：2000-06-27
申请人： Sandor A. Frecska , John E. Cronin
发明人： Sandor A. Frecska , John E. Cronin
IPC分类号： H05K500
CPC分类号： E04B9/045 , E04B9/0457 , H01Q1/007 , H01Q1/1207 , H01Q1/40 , H01Q1/44 , H01Q23/00
摘要： A ceiling tile transmitter and receiver system having at least one transmitter/receiver device located in a ceiling panel either during or after the ceiling panel fabrication process. In one embodiment one or more pockets of variable size and shape are created on a surface of the ceiling panel during or after the ceiling panel manufacturing process and then a transmitter/receiver device, such as an RF antenna, is inserted in the pocket. In another embodiment, the transmitter/receiver device is embedded in the front side (lower surface) of the ceiling tile and a “scrim” covering is placed over it to secure it in place. The transmitter/receiver device can also be embedded inside the ceiling tile or on an upper, lower or side surface of the ceiling tile. Various combinations of these embodiments can be used with a single ceiling tile. A high temperature resistant “place holding” structure that can withstand the ceiling tile treatments can be provided and later removed to allow the installation of the transmitter/receiver device.
摘要翻译：天花板发射器和接收器系统在顶板制造过程中或之后具有位于天花板面板中的至少一个发射器/接收器装置。在一个实施例中，在天花板面板制造过程期间或之后，在天花板面的表面上形成可变尺寸和形状的一个或多个口袋，然后将诸如RF天线的发射机/接收机设备插入口袋中。在另一个实施例中，发射机/接收机设备嵌入在天花板瓦片的前侧（下表面）中，并且在其上放置“稀松布”覆盖物以将其固定就位。发射器/接收器装置也可嵌入天花板瓦片或天花板瓦片的上，下或侧表面。这些实施例的各种组合可以与单个天花板瓦片一起使用。可以提供可以承受天花板处理的耐高温“占位”结构，并且稍后移除以允许安装发射机/接收机设备。

45. 发明授权

US06391661B2 Semiconductor and method of fabricating 失效
标题翻译：半导体及其制造方法
公开(公告)号：US06391661B2
公开(公告)日：2002-05-21
申请号：US09785181
申请日：2001-02-20
申请人： Daniel S. Brooks , Phillip F. Chapman , John E. Cronin , Richard E. Wistrom
发明人： Daniel S. Brooks , Phillip F. Chapman , John E. Cronin , Richard E. Wistrom
IPC分类号： H01L2100
CPC分类号： H01L21/28017 , H01L21/28176 , H01L21/28194 , H01L21/28211 , H01L21/28247
摘要： Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.
摘要翻译：提供一种包括基板的半导体结构; 指挥以及将导体与基板分离的绝缘层; 以及耦合到所述导体和所述衬底的可移除导电带，用于在离子束和/或等离子体处理期间在所述导体和衬底之间维持公共电压; 和制造方法。

46. 发明授权

US6137129A High performance direct coupled FET memory cell 失效
标题翻译：高性能直接耦合FET存储单元
公开(公告)号：US6137129A
公开(公告)日：2000-10-24
申请号：US2825
申请日：1998-01-05
申请人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
发明人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
IPC分类号： H01L21/8244 , H01L27/11 , H01L27/108 , H01L29/74 , H01L29/76
CPC分类号： H01L27/11 , Y10S257/903
摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.
摘要翻译：一对直接耦合的场效应晶体管（FET），直接耦合FETS的锁存器，包括直接耦合FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元。可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。每个设备的门是该对的另一个设备的源或漏极。优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。优选实施例SRAM过程具有三个主要步骤。首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。第二，在传输门或输入/输出（I / O）层上形成单元传输门。第三，I / O层被粘合并连接到优选的锁存层。

47. 发明授权

US5567653A Process for aligning etch masks on an integrated circuit surface using electromagnetic energy 失效
标题翻译：使用电磁能量在集成电路表面上对准蚀刻掩模的工艺
公开(公告)号：US5567653A
公开(公告)日：1996-10-22
申请号：US306042
申请日：1994-09-14
申请人： Claude L. Bertin , John E. Cronin , David J. Perlman
发明人： Claude L. Bertin , John E. Cronin , David J. Perlman
IPC分类号： H01L25/00 , H01L21/98 , H01L23/52 , H01L25/065 , H01L21/027 , H01L21/31
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/13022 , H01L2225/06524 , H01L2225/06551 , H01L2225/06593 , H01L2225/06596 , H01L2924/10253 , Y10S438/928 , Y10S438/975 , Y10S438/977
摘要： Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
摘要翻译：用于堆叠集成电路芯片和所得三维半导体结构的对准的方法。根据需要在每个集成电路芯片上沉积厚度控制层。该层的厚度由在制造过程中的研磨阶段之后的芯片的厚度确定。互补图案蚀刻到每个芯片的厚度控制层中并进入相邻的芯片。在三维结构中堆叠芯片时，对于布置在每个集成电路芯片的边缘上的互连焊盘，获得精确的对准。因此，可以在所得到的三维结构的表面上支持密集的总线和I / O网络。

48. 发明授权

US5539255A Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal 失效
标题翻译：具有由单层金属形成的自对准互连金属化的半导体结构
公开(公告)号：US5539255A
公开(公告)日：1996-07-23
申请号：US524558
申请日：1995-09-07
申请人： John E. Cronin
发明人： John E. Cronin
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L23/485
CPC分类号： H01L21/76897 , H01L21/76877 , H01L23/5226 , H01L2924/0002
摘要： An improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-up and interconnection line are formed from a single layer of metal. The structure is prepared by a method in which an insulator region is first provided on a semiconductor substrate, and is then patterned and etched to define at least one opening having a pre-selected depth. Metal is deposited to fill the opening and form the interconnection line, followed by the patterning and formation of a stud-up of desired dimensions within the metal-filled opening. The lower end of the stud-up becomes connected to the interconnection line, and the upper end of the stud-up terminates at or near the upper surface of the insulator region. Other embodiments also include an interconnected stud-down.An endpoint detection technique can be used to precisely control the height of the stud-up and the width of the interconnection line.
摘要翻译：公开了一种改进的半导体结构，其包括至少一个连接线和与之连接的互连线，其中分离线和互连线由单层金属形成。该结构通过首先在半导体衬底上提供绝缘体区域的方法制备，然后将其图案化和蚀刻以限定具有预选深度的至少一个开口。金属沉积以填充开口并形成互连线，随后在金属填充的开口内形成图案并形成所需尺寸的分层。分支的下端连接到互连线，并且分支的上端终止于或靠近绝缘体区域的上表面。其他实施例还包括互连的分离。端点检测技术可以用于精确控制分支的高度和互连线的宽度。

49. 发明授权

US5532519A Cube wireability enhancement with chip-to-chip alignment and thickness control 失效
标题翻译：具有芯片对芯片对齐和厚度控制的立方线可提升性
公开(公告)号：US5532519A
公开(公告)日：1996-07-02
申请号：US375770
申请日：1995-01-20
申请人： Claude L. Bertin , John E. Cronin , David J. Perlman
发明人： Claude L. Bertin , John E. Cronin , David J. Perlman
IPC分类号： H01L25/00 , H01L21/98 , H01L23/52 , H01L25/065 , H01L23/538
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/13022 , H01L2225/06524 , H01L2225/06551 , H01L2225/06593 , H01L2225/06596 , H01L2924/10253 , Y10S438/928 , Y10S438/975 , Y10S438/977
摘要： Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
摘要翻译：用于堆叠集成电路芯片和所得三维半导体结构的对准的方法。根据需要在每个集成电路芯片上沉积厚度控制层。该层的厚度由在制造过程中的研磨阶段之后的芯片的厚度确定。互补图案蚀刻到每个芯片的厚度控制层中并进入相邻的芯片。在三维结构中堆叠芯片时，对于布置在每个集成电路芯片的边缘上的互连焊盘，获得精确的对准。因此，可以在所得到的三维结构的表面上支持密集的总线和I / O网络。

50. 发明授权

US5213916A Method of making a gray level mask 失效
标题翻译：制作灰度掩码的方法
公开(公告)号：US5213916A
公开(公告)日：1993-05-25
申请号：US605606
申请日：1990-10-30
申请人： John E. Cronin , Paul A. Farrar, Sr. , Carter W. Kaanta , James G. Ryan , Andrew J. Watts
发明人： John E. Cronin , Paul A. Farrar, Sr. , Carter W. Kaanta , James G. Ryan , Andrew J. Watts
IPC分类号： G03F1/00 , G03F7/00 , G03F9/00 , H01L21/027
CPC分类号： G03F7/0035 , G03F1/50
摘要： A gray level mask suitable for photolithography is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. The mask is fabricated with the aid of a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist, the metal of one of the layers, and the glass of the other of the layers. The etches include plasma etch with chloride ions to attack the chromium of the opaque layer, compounds of fluorine to attack the glass layer, and reactive ion etching with oxygen to attack the photoresist structure. Also, developer is employed for etching on hardened regions of resist in the photoresist structure.
摘要翻译：适用于光刻的灰度级掩模由透明玻璃基板构成，该透明玻璃基板支持具有不同透光率的多层材料。在仅使用这些水平中的两个的掩模的情况下，一个层可以由通过取代银离子代替在玻璃的结构中使用的碱金属硅酸盐的金属离子而部分透射的玻璃构成。第二层可以通过金属如铬的构造而变得不透明。借助于光致抗蚀剂结构制造掩模，该光致抗蚀剂结构通过光刻掩模在特定区域中被蚀刻，以使得能够选择性地蚀刻具有不同光学透射率的材料层的暴露区域。各种蚀刻用于选择性蚀刻光致抗蚀剂，其中一层的金属和另一层的玻璃。蚀刻包括用氯离子等离子体蚀刻以侵蚀不透明层的铬，氟的化合物侵蚀玻璃层，以及用氧反应离子蚀刻以侵蚀光致抗蚀剂结构。此外，显影剂用于蚀刻光致抗蚀剂结构中的抗蚀剂的硬化区域。

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