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41. 发明申请

US20090004856A1 METHOD OF FORMING CONTACT PLUG IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中形成接触片的方法
公开(公告)号：US20090004856A1
公开(公告)日：2009-01-01
申请号：US11950500
申请日：2007-12-05
申请人： Eun Soo Kim , Jung Geun Kim , Seung Hee Hong
发明人： Eun Soo Kim , Jung Geun Kim , Seung Hee Hong
IPC分类号： H01L21/44
CPC分类号： H01L21/76832 , H01L21/31116 , H01L21/76814 , H01L21/76816
摘要： A method of forming a contact plug in a semiconductor device comprising etching an interlayer insulating layer to form a patterned interlayer insulating layer having contact holes such that a distance between upper portions of the contact holes is minimized; forming a first insulating layer including a overhang portion for wrapping an upper portion of the patterned interlayer insulating layer; forming a liner-shaped second insulating layer on the patterned interlayer insulating layer including the first insulating layer, the second insulating layer being formed from material having a selectivity which differs from that of the first insulating layer; and at least partially removing the second insulating layer to increase a bottom critical dimension of the contact hole and removing the overhang portion of the first insulating layer. The invention can secure the bottom critical dimension of the contact hole as well as a distance between the upper portions of the contact holes when the contact plug is formed in a trench in a subsequent process so that the subsequent process margin can be secured. Also, the invention can inhibit an overhang or seam from being formed on the contact plug to enhance contact gap-fill capability and improve contact resistance.
摘要翻译：一种在半导体器件中形成接触插塞的方法，包括蚀刻层间绝缘层以形成具有接触孔的图案化层间绝缘层，使得接触孔的上部之间的距离最小化; 形成第一绝缘层，所述第一绝缘层包括用于缠绕所述图案化层间绝缘层的上部的突出部分; 在包括所述第一绝缘层的所述图案化层间绝缘层上形成衬垫状第二绝缘层，所述第二绝缘层由与所述第一绝缘层的选择性不同的材料形成; 并且至少部分地去除第二绝缘层以增加接触孔的底部临界尺寸并去除第一绝缘层的突出部分。本发明可以确保接触孔的底部临界尺寸以及接触孔的上部在接下来的过程中在沟槽中形成接触塞时的距离，从而可以确保随后的加工余量。此外，本发明可以抑制在接触插塞上形成的突出端或接缝，以增强接触间隙填充能力并提高接触电阻。

42. 发明申请

US20090023279A1 METHOD OF FABRICATING FLASH MEMORY DEVICE 失效
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20090023279A1
公开(公告)日：2009-01-22
申请号：US12131626
申请日：2008-06-02
申请人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
发明人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/311 , H01L21/28
CPC分类号： H01L21/764 , H01L27/115 , H01L27/11521
摘要： The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented.
摘要翻译：本发明涉及一种制造闪速存储器件的方法，包括在字线和浮栅之间形成具有低介电常数的气隙。此外，在用于控制栅极的钨（W）层的侧壁上形成氮化钨（WN）层。因此，可以提高最终形成的控制栅极的横截面，同时防止随后的退火工艺中钨层的异常氧化。本发明的方法可以改善相邻字线之间的干扰，从而提高设备的可靠性。因此，可以实现鲁棒的高速设备。

43. 发明授权

US07033907B2 Method for forming isolation layer of semiconductor device 有权
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US07033907B2
公开(公告)日：2006-04-25
申请号：US10878451
申请日：2004-06-28
申请人： Jung Geun Kim
发明人： Jung Geun Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/76229
摘要： A method for forming an isolation layer of a semiconductor device is disclosed, which comprises the steps of: etching a silicon substrate having a cell region and a peripheral circuit region, forming a first trench having a first size in the cell region, and forming a second trench having a second size, which is larger than the first size of the first trench, in the peripheral circuit region; forming a sidewall oxide layer on surfaces of the first trench and the second trench; sequentially depositing a liner nitride layer and a liner oxide layer on a resultant substrate inclusive of the sidewall oxide layer; performing a plasma pre-heating process using O2+He with respect to the resultant substrate in an HDP CVD process chamber and selectively oxidizing a portion of the liner nitride layer remaining on a bottom of the second trench in the peripheral circuit region; continuously depositing an HDP oxide layer on the resultant substrate having been subjected to the plasma pre-heating process, thereby filling the trenches; and performing a chemical mechanical polishing process with respect to the HDP oxide layer.
摘要翻译：公开了一种用于形成半导体器件的隔离层的方法，其包括以下步骤：蚀刻具有单元区域和外围电路区域的硅衬底，在单元区域中形成具有第一尺寸的第一沟槽，并形成在外围电路区域中具有大于第一沟槽的第一尺寸的第二尺寸的第二沟槽; 在所述第一沟槽和所述第二沟槽的表面上形成侧壁氧化物层; 在包括侧壁氧化物层的所得衬底上依次沉积衬里氮化物层和衬垫氧化物层; 在HDP CVD处理室中使用O 2 H 2 He对所得衬底进行等离子体预热处理，并且选择性地氧化残留在第二沟槽的底部上的衬里氮化物层的一部分外围电路区域; 在经过等离子体预热处理的所得基板上连续沉积HDP氧化物层，从而填充沟槽; 对HDP氧化物层进行化学机械研磨处理。

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