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    • 42. 发明授权
      US06372586B1 Method for LDMOS transistor with thick copper interconnect 有权
    • Method for LDMOS transistor with thick copper interconnect
    • 具有厚铜互连的LDMOS晶体管的方法
    • US06372586B1
    • 2002-04-16
    • US09566956
    • 2000-05-08
    • Taylor R. Efland , Dave Cotton , Dale J. Skelton
    • Taylor R. Efland , Dave Cotton , Dale J. Skelton
    • H01L21331
    • H01L29/7835 , H01L23/4824 , H01L23/53228 , H01L29/0696 , H01L29/41725 , H01L29/41758 , H01L29/41775 , H01L29/456 , H01L29/7801 , H01L2924/0002 , H01L2924/00
    • A thick copper interconnection structure and method for an LDMOS transistor for power semiconductor devices. A large LDMOS transistor is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain. Gate regions are formed between the alternating source and drain diffusions. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a source and a drain bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive copper layer. The thick third level metal bus substantially lowers the resistance of the LDMOS transistor and further eliminates current debiasing and early failure location problems experienced with LDMOS transistors of the prior art. Other devices and methods are described.
    • 用于功率半导体器件的LDMOS晶体管的厚铜互连结构和方法。 大的LDMOS晶体管由多个源极和漏极扩散区域形成以耦合在一起以形成源极和漏极。 栅极区域形成在交替的源极和漏极扩散之间。 每个扩散区具有形成在其上并与其电接触的第一金属层条纹。 第二金属层导体形成在多个第一金属层条纹上，并且选择性地接触第一金属层条纹以形成源极和漏极总线。 然后在每个第二金属层母线上形成厚的第三金属层，或者物理地接触它或选择性地电接触它。 厚三层金属由高导电铜层制成。 厚的第三级金属总线大大降低了LDMOS晶体管的电阻，并进一步消除了现有技术的LDMOS晶体管所经历的电流去差和早期故障定位问题。 描述其他设备和方法。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 43. 发明授权
      US06274918B1 Integrated circuit diode, and method for fabricating same 有权
    • Integrated circuit diode, and method for fabricating same
    • 集成电路二极管及其制造方法
    • US06274918B1
    • 2001-08-14
    • US09252171
    • 1999-02-18
    • Chin-Yu Tsai , Taylor R. Efland
    • Chin-Yu Tsai , Taylor R. Efland
    • H01L2358
    • H01L27/0635 , H01L29/0615 , H01L29/0692 , H01L29/866
    • An integrated circuit (10) includes a P-epi substrate (12) having therein an n-well isolation layer (13) and a p-well (14) within the n-well. The p-well includes adjacent an upper surface thereof a p+ layer (18) having several elongate parallel openings (21-23) therethrough. Each of the openings has therein a respective n− RESURF layer (26-28). Each n− RESURF layer has therethrough a respective further elongate opening (31-33), and has a uniform horizontal thickness all around that opening. Each of the openings in the RESURF layers has therein an n+ finger (36-38). The p+ layer and the n+ fingers each have a vertical thickness which is greater than the vertical thickness of the n− RESURF layers. The p+ layer serves as the anode of a zener diode, and the n+ fingers are interconnected and serve as the cathode.
    • 集成电路（10）包括在n阱内具有n阱隔离层（13）和p阱（14）的P外延衬底（12）。 p阱包括邻近其上表面的具有多个细长的平行开口（21-23）的p +层（18）。 每个开口都具有相应的n-RESURF层（26-28）。 每个n-RESURF层具有相应的另外的细长开口（31-33），并且在该开口周围具有均匀的水平厚度。 RESURF层中的每个开口均具有n +指（36-38）。 p +层和n +指各自具有大于n-RESURF层的垂直厚度的垂直厚度。 p +层用作齐纳二极管的阳极，并且n +指状物互连并用作阴极。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 46. 发明授权
      US5859456A Multiple transistor integrated circuit with thick copper interconnect 失效
    • Multiple transistor integrated circuit with thick copper interconnect
    • 具有厚铜互连的多晶体管集成电路
    • US5859456A
    • 1999-01-12
    • US711138
    • 1996-09-09
    • Taylor R. Efland , David Cotton , Dale J. Skelton
    • Taylor R. Efland , David Cotton , Dale J. Skelton
    • H01L21/822 , H01L21/336 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/417 , H01L29/78 , H01L29/866 , H01L27/08
    • H01L29/7835 , H01L29/41758 , H01L29/7801
    • An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form source and drain busses. Polysilicon gate busses are provided as well. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting on resistance for the transistors on the integrated circuit is substantially reduced by the use of the thick third metal layer. Current debiasing and electromigration problems of the prior art are reduced or eliminated. A seven transistor integrated circuit formed from power transistors and incorporating the invention is described. Other devices, systems and methods are also disclosed.
    • 公开了一种用于多晶体管集成电路功率器件的互连结构和方法。 功率集成电路由多个源极和漏极扩散区域形成以耦合在一起以形成多个LDMOS晶体管的源极和漏极。 每个扩散区具有形成在其上并与其电接触的第一金属层条纹。 第二金属层导体形成在多个第一金属层条纹上，并且选择性地接触第一金属层条纹以形成源极和漏极总线。 也提供多晶硅栅母线总线。 然后在每个第二金属层母线上形成厚的第三金属层，或者物理地接触它或选择性地电接触它。 厚的第三级金属由诸如铜的高导电材料制成。 通过使用厚的第三金属层，集成电路上的晶体管的导通电阻大大降低。 减少或消除了现有技术的当前的去噪和电迁移问题。 描述了由功率晶体管形成并结合本发明的七晶体管集成电路。 还公开了其他装置，系统和方法。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 47. 发明授权
      US5728594A Method of making a multiple transistor integrated circuit with thick copper interconnect 失效
    • Method of making a multiple transistor integrated circuit with thick copper interconnect
    • 制造具有厚铜互连的多晶体管集成电路的方法
    • US5728594A
    • 1998-03-17
    • US474621
    • 1995-06-07
    • Taylor R. Efland , David Cotton , Dale J. Skelton
    • Taylor R. Efland , David Cotton , Dale J. Skelton
    • H01L21/822 , H01L21/336 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/417 , H01L29/78 , H01L29/866 , H01L21/265
    • H01L29/7835 , H01L29/41758 , H01L29/7801
    • An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form source and drain busses. Polysilicon gate busses are provided as well. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting on resistance for the transistors on the integrated circuit is substantially reduced by the use of the thick third metal layer. Current debiasing and electromigration problems of the prior art are reduced or eliminated. A seven transistor integrated circuit formed from power transistors and incorporating the invention is described. Other devices, systems and methods are also disclosed.
    • 公开了一种用于多晶体管集成电路功率器件的互连结构和方法。 功率集成电路由多个源极和漏极扩散区域形成以耦合在一起以形成多个LDMOS晶体管的源极和漏极。 每个扩散区具有形成在其上并与其电接触的第一金属层条纹。 第二金属层导体形成在多个第一金属层条纹上，并且选择性地接触第一金属层条纹以形成源极和漏极总线。 也提供多晶硅栅母线总线。 然后在每个第二金属层母线上形成厚的第三金属层，或者物理地接触它或选择性地电接触它。 厚的第三级金属由诸如铜的高导电材料制成。 通过使用厚的第三金属层，集成电路上的晶体管的导通电阻大大降低。 减少或消除了现有技术的当前的去噪和电迁移问题。 描述了由功率晶体管形成并结合本发明的七晶体管集成电路。 还公开了其他装置，系统和方法。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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