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41. 发明授权

US08212218B2 Dosimeter powered by passive RF absorption 有权
标题翻译：剂量计由被动射频吸收提供动力
公开(公告)号：US08212218B2
公开(公告)日：2012-07-03
申请号：US12627076
申请日：2009-11-30
申请人： Cyril Cabral, Jr. , Michael S. Gordon , Steven J. Koester , Conal E. Murray , Kenneth P. Rodbell , Stephen M. Rossnagel , Robert L. Wisnieff , Jeng-bang Yau
发明人： Cyril Cabral, Jr. , Michael S. Gordon , Steven J. Koester , Conal E. Murray , Kenneth P. Rodbell , Stephen M. Rossnagel , Robert L. Wisnieff , Jeng-bang Yau
IPC分类号： G01T1/02
CPC分类号： G01T1/026
摘要： A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency.
摘要翻译：用于确定辐射量的系统包括配置成接收辐射量的剂量计，该剂量计包括具有谐振频率的电路，使得电路的谐振频率根据剂量计接收的辐射量而改变，剂量计还被配置为吸收电路的谐振频率处的RF能量; 射频（RF）发射器，被配置为以共振频率将所述RF能量传输到所述剂量计; 以及接收器，被配置为基于所吸收的RF能量来确定所述剂量计的谐振频率，其中所述辐射量基于所述谐振频率来确定。

42. 发明申请

US20120149173A1 3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL 有权
标题翻译：具有精密可控底板拆卸的3D集成电路设备制造
公开(公告)号：US20120149173A1
公开(公告)日：2012-06-14
申请号：US13398481
申请日：2012-02-16
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
IPC分类号： H01L21/30
CPC分类号： H01L27/105 , H01L24/11 , H01L27/0688 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/0557 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。根据该方法，提供第一有源电路层晶片。第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分。接下来，在P-层的背面上制造布线层。还提供了编码有用于制造3D集成电路结构的程序的非暂时计算机可读介质，以及3D集成电路结构。

43. 发明申请

US20110233785A1 BACKSIDE DUMMY PLUGS FOR 3D INTEGRATION 有权
标题翻译：用于3D集成的备用DUMMY PLUGS
公开(公告)号：US20110233785A1
公开(公告)日：2011-09-29
申请号：US12730403
申请日：2010-03-24
申请人： Steven J. Koester , Fei Liu
发明人： Steven J. Koester , Fei Liu
IPC分类号： H01L23/538 , H01L21/768 , H01L21/50
CPC分类号： H01L24/05 , H01L21/7682 , H01L21/76898 , H01L23/3677 , H01L23/481 , H01L23/585 , H01L24/08 , H01L24/80 , H01L2224/02372 , H01L2224/0401 , H01L2224/05024 , H01L2224/05094 , H01L2224/05095 , H01L2224/0557 , H01L2224/08145 , H01L2224/80006 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01327 , H01L2924/12044 , H01L2924/1301 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor structure includes backside dummy plugs embedded in a substrate. The backside dummy plugs can be a conductive structure that enhances vertical thermal conductivity of the semiconductor structure and provides electrical decoupling of signals in through-substrate vias (TSVs) in the substrate. The backside dummy plug can include a cavity to accommodate volume changes in other components in the substrate, thereby alleviating mechanical stress in the substrate during thermal cycling and operation of the semiconductor chip. The backside dummy plug including the cavity can be composed of an insulator material or a conductive material. The inventive structures can be employed to form three-dimensional structures having vertical chip integration, in which inter-wafer thermal conductivity is enhanced, cross-talk between signals through TSVs is reduced, and/or mechanical stress to the TSVs is reduced.
摘要翻译：半导体结构包括嵌入基板中的背面虚拟插头。背面虚拟插头可以是导电结构，其增强了半导体结构的垂直导热性并且提供了在衬底中的贯穿衬底通孔（TSV）中的信号的电去耦合。背面虚拟插头可以包括空腔以适应衬底中的其他部件的体积变化，从而在半导体芯片的热循环和操作期间减轻衬底中的机械应力。包括空腔的背面虚拟插头可以由绝缘体材料或导电材料构成。本发明的结构可以用于形成具有垂直芯片集成的三维结构，其中晶片间热导率提高，通过TSV的信号之间的串扰减少，和/或对TSV的机械应力降低。

44. 发明授权

US07871869B2 Extremely-thin silicon-on-insulator transistor with raised source/drain 有权
标题翻译：极薄的绝缘体上硅晶体管，具有升高的源极/漏极
公开(公告)号：US07871869B2
公开(公告)日：2011-01-18
申请号：US12543679
申请日：2009-08-19
申请人： Eduard A. Cartier , Steven J. Koester , Kingsuk Maitra , Amlan Majumdar , Renee T. Mo
发明人： Eduard A. Cartier , Steven J. Koester , Kingsuk Maitra , Amlan Majumdar , Renee T. Mo
IPC分类号： H01L21/00
CPC分类号： H01L29/6659 , H01L21/28079 , H01L29/4958 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6656 , H01L29/66628 , H01L29/66772 , H01L29/78696
摘要： An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.
摘要翻译：提供了一种极薄的绝缘体上硅晶体管，其包括衬底上的掩埋氧化物层，掩埋氧化物层上方的硅层，硅层上的栅极堆叠，硅层上的氮化物衬垫，栅堆叠，氮化物衬垫上并与其相邻的氧化物衬垫，以及升高的源/漏区。栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。凸起的源极/漏极区域中的每一个具有包括硅层的一部分的第一部分，与氧化物衬垫和氮化物衬垫的部分相邻的第二部分，以及在第二部分上方的第三部分。还提供了制造极薄的绝缘体上硅晶体管的方法。

45. 发明申请

US20090325358A1 METHOD OF REDUCING DISLOCATION-INDUCED LEAKAGE IN A STRAINED-LAYER FIELD-EFFECT TRANSISTOR 有权
标题翻译：降低应变层场效应晶体管中的分解诱导漏电的方法
公开(公告)号：US20090325358A1
公开(公告)日：2009-12-31
申请号：US12539235
申请日：2009-08-11
申请人： Steven J. Koester
发明人： Steven J. Koester
IPC分类号： H01L21/322 , H01L21/336
CPC分类号： H01L29/78 , H01L21/26506 , H01L21/26513 , H01L29/1041 , H01L29/1054 , H01L29/51 , H01L29/517 , H01L29/518
摘要： A structure and method of fabricating a semiconductor field-effect transistor (MOSFET) such as a strained Si n-MOSFET where dislocation or crystal defects spanning from source to drain is partially occupied by heavy p-type dopants. Preferably, the strained-layer n-MOSFET includes a Si, SiGe or SiGeC multi-layer structure having, in the region between source and drain, impurity atoms that preferentially occupy the dislocation sites so as to prevent shorting of source and drain via dopant diffusion along the dislocation. Advantageously, devices formed as a result of the invention are immune to dislocation-related failures, and therefore are more robust to processing and material variations. The invention thus relaxes the requirement for reducing the threading dislocation density in SiGe buffers, since the devices will be operable despite the presence of a finite number of dislocations.
摘要翻译：制造诸如应变Si n-MOSFET的半导体场效应晶体管（MOSFET）的结构和方法，其中跨越源极到漏极的位错或晶体缺陷部分地被重的p型掺杂剂占据。优选地，应变层n-MOSFET包括在源极和漏极之间的区域中具有优先占据位错位置的杂质原子的Si，SiGe或SiGeC多层结构，以便防止源极和漏极通过掺杂剂扩散而短路沿错位。有利地，作为本发明的结果形成的装置不受位错相关的故障的影响，因此对于处理和材料变化更加鲁棒。因此，本发明放松了降低SiGe缓冲器中的穿透位错密度的要求，因为即使存在有限数量的位错，器件也将是可操作的。

46. 发明申请

US20090311836A1 EXTREMELY-THIN SILICON-ON-INSULATOR TRANSISTOR WITH RAISED SOURCE/DRAIN 有权
公开(公告)号：US20090311836A1
公开(公告)日：2009-12-17
申请号：US12543679
申请日：2009-08-19
申请人： EDUARD A. CARTIER , Steven J. Koester , Kingsuk Maitra , Arnlan Majumdar , Renee T. Mo
发明人： EDUARD A. CARTIER , Steven J. Koester , Kingsuk Maitra , Arnlan Majumdar , Renee T. Mo
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/28079 , H01L29/4958 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6656 , H01L29/66628 , H01L29/66772 , H01L29/78696
摘要： An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.

47. 发明授权

US07510904B2 Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector 有权
标题翻译：制造高速CMOS兼容的绝缘体上的光电探测器的结构和方法
公开(公告)号：US07510904B2
公开(公告)日：2009-03-31
申请号：US11556739
申请日：2006-11-06
申请人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiqing Ouyang , Jeremy D. Schaub
发明人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiqing Ouyang , Jeremy D. Schaub
IPC分类号： H01L21/00
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.
摘要翻译：本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。该器件通过利用掩埋绝缘层，通过利用Ge吸收层，利用薄的吸收层和窄电极间隔的低电压操作以及兼容性来兼容宽泛的光谱，利用埋入的绝缘层来隔离底层衬底中产生的载流子，通过其平面结构和使用IV族吸收材料的CMOS器件。用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。

48. 发明授权

US06972250B2 Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device 失效
标题翻译：通过垂直自对准CoSi2在升高的源极漏极Si / SiGe器件上形成的超低接触电阻CMOS的方法和结构
公开(公告)号：US06972250B2
公开(公告)日：2005-12-06
申请号：US10419888
申请日：2003-04-22
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
IPC分类号： H01L21/285 , H01L21/336 , H01L21/8238 , H01L29/161 , H01L21/4763
CPC分类号： H01L29/41783 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/161 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.
摘要翻译：形成垂直自对准的硅化物接触到下面的SiGe层的方法（和结构）包括在SiGe层上形成第一预定厚度的硅层，并在硅层上形成一层金属，其中金属层具有第二预定厚度。然后在预定温度下的热退火工艺形成硅和金属的硅化物，其中选择预定温度以基本排除硅化物渗入下面的SiGe层。

49. 发明授权

US06805962B2 Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications 有权
标题翻译：为应变Si CMOS应用创造高品质松弛SiGe绝缘体的方法
公开(公告)号：US06805962B2
公开(公告)日：2004-10-19
申请号：US10055138
申请日：2002-01-23
申请人： Stephen W. Bedell , Jack O. Chu , Keith E. Fogel , Steven J. Koester , Devendra K. Sadana , John Albrecht Ott
发明人： Stephen W. Bedell , Jack O. Chu , Keith E. Fogel , Steven J. Koester , Devendra K. Sadana , John Albrecht Ott
IPC分类号： B32B900
CPC分类号： H01L21/76243 , H01L21/02378 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02612 , H01L21/2251 , H01L21/324 , H01L27/1203 , H01L29/66916 , Y10S438/938 , Y10T428/12674 , Y10T428/265 , Y10T428/31848
摘要： A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to the diffusion of Ge. Optionally forming a Si cap layer over the SiGe or pure Ge layer, and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughout the first single crystal Si layer, the optional Si cap and the SiGe or pure Ge layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate materials are also disclosed herein.
摘要翻译：提供一种形成薄的，高质量的松散的绝缘体上硅衬底材料的方法，其首先包括在第一单晶Si层的表面上形成SiGe或纯Ge层，该第一单晶Si层存在于阻挡层上对Ge的扩散。可选择地在SiGe或纯Ge层上形成Si覆盖层，然后在允许Ge遍及第一单晶Si层的相互扩散的温度下加热各层，任选的Si盖和SiGe或纯Ge层，从而形成基本上松弛的单晶SiGe层在阻挡层顶上。附加的SiGe再生长和/或应变外延层的形成可以遵循上述步骤。绝缘体上硅衬底材料以及至少包括绝缘体上硅衬底材料的结构也在本文中公开。

50. 发明授权

US09178061B2 Method for fabricating MOSFET on silicon-on-insulator with internal body contact 有权
标题翻译：用于在绝缘体上制造具有内部接触的绝缘体上的MOSFET的方法
公开(公告)号：US09178061B2
公开(公告)日：2015-11-03
申请号：US13572039
申请日：2012-08-10
申请人： Jin Cai , Steven J. Koester , Amlan Majumdar
发明人： Jin Cai , Steven J. Koester , Amlan Majumdar
IPC分类号： H01L21/28 , H01L21/44 , H01L29/78 , H01L29/08 , H01L29/417 , H01L29/66 , H01L29/786
CPC分类号： H01L29/0847 , H01L29/41733 , H01L29/66659 , H01L29/7835 , H01L29/78612 , H01L29/78621
摘要： A method is provided for fabricating a semiconductor device. According to the method, a semiconductor layer is formed over a semiconductor-on-insulator substrate, and a gate is formed on the semiconductor layer. Source and drain extension regions and a deep drain region are formed in the semiconductor layer. A deep source region is formed in the semiconductor layer. A drain metal-semiconductor alloy contact is located on the upper portion of the deep drain region and abutting the drain extension region. A source metal-semiconductor alloy contact abuts the source extension region. The deep source region is located below and contacts a first portion of the source metal-semiconductor alloy contact. The deep source region is not located below and does not contact a second portion of the source metal-semiconductor alloy contact. The second portion of the source metal-semiconductor alloy contact is an internal body contact that directly contacts the semiconductor layer.
摘要翻译：提供了制造半导体器件的方法。根据该方法，在绝缘体上半导体基板上形成半导体层，在半导体层上形成栅极。源极和漏极延伸区域和深的漏极区域形成在半导体层中。在半导体层中形成深源区。漏极金属 - 半导体合金触点位于深漏区域的上部并邻接漏极延伸区域。源极金属 - 半导体合金接触件邻接源极延伸区域。深源区域位于源极金属 - 半导体合金接触件的第一部分下方并接触。深源区不位于源极金属 - 半导体合金触点的第二部分下方并且不接触。源极金属 - 半导体合金触点的第二部分是直接接触半导体层的内部主体接触。

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