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41. 发明申请

US20080142861A1 SYMMETRIC CAPACITOR STRUCTURE 审中-公开
标题翻译：对称电容结构
公开(公告)号：US20080142861A1
公开(公告)日：2008-06-19
申请号：US12029748
申请日：2008-02-12
申请人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L29/94
CPC分类号： H01L27/0805
摘要： A structure comprising a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.
摘要翻译：一种包括形成在衬底内的第一掺杂区，第二掺杂区，第三掺杂区和第一浅沟槽隔离结构的结构。第一掺杂区域包括具有第一极性的第一掺杂剂。第二掺杂区域形成电容器的第一电极。第三掺杂区域形成电容器的第二电极。第二掺杂区域和第三掺杂区域中的每一个包括具有第二极性的第二掺杂剂。第一浅沟槽隔离结构形成在第二掺杂区和第三掺杂区之间。电容器包括主电容。该结构包括第一寄生电容和第二寄生电容。第一寄生电容约等于第二寄生电容。

42. 发明授权

US09448162B2 Time-resolved single-photon or ultra-weak light multi-dimensional imaging spectrum system and method 有权
标题翻译：时间分辨单光子或超弱光多维成像光谱系统及方法
公开(公告)号：US09448162B2
公开(公告)日：2016-09-20
申请号：US14351028
申请日：2012-05-14
申请人： Guangjie Zhai , Wenkai Yu , Xuefeng Liu , Xuri Yao , Chao Wang , Zhibin Sun
发明人： Guangjie Zhai , Wenkai Yu , Xuefeng Liu , Xuri Yao , Chao Wang , Zhibin Sun
IPC分类号： G01N21/25 , G01N21/64 , G01N21/17 , H03K21/38 , G01J1/04 , G01J1/42 , G01S17/89 , G01S7/481 , G01S7/486 , G02B26/08
CPC分类号： G01N21/255 , G01J1/0414 , G01J1/4228 , G01N21/17 , G01N21/6456 , G01S7/4816 , G01S7/486 , G01S17/89 , G02B26/0833 , H03K21/38
摘要： A single-photon or ultra-weak light multi-D imaging spectral system and method. In order to realize rough time resolution, a time-resolved single-photon counting 2D imaging system for forming color or grey imaging is provided. Moreover, in order to realize high-precision time resolution, the system comprises a light source, an imaging spectral measurement unit, an electric detection unit, a system control unit and an algorithm unit. The light carrying information of an object is imaged on a spatial light modulator and randomly modulated according to compressed sensing theory, emergent light of a grating is collected using a point or array single-photon detector, the number of photons and photon arrival time are recorded, and reconstruction is carried out using the compressed sensing algorithm and related algorithm of the spectral imaging. The system provides single-photon detection sensitivity, high time resolution and wide spectral range, and can be applied in numerous new high-tech industries.
摘要翻译：单光子或超弱光多D成像光谱系统及方法。为了实现粗糙的时间分辨率，提供了用于形成彩色或灰度成像的时间分辨的单光子计数2D成像系统。此外，为了实现高精度时间分辨率，该系统包括光源，成像光谱测量单元，电检测单元，系统控制单元和算法单元。物体的光携带信息在空间光调制器上成像，并且根据压缩感测理论随机调制，使用点或阵列单光子检测器收集光栅的出射光，记录光子数和光子到达时间，并利用压缩感知算法和相关的光谱成像算法进行重建。该系统提供单光子检测灵敏度高，时间分辨率高，光谱范围广，可应用于众多新兴高科技行业。

43. 发明授权

US09080990B2 Illumination subsystems of a metrology system, metrology systems, and methods for illuminating a specimen for metrology measurements 有权
标题翻译：计量系统的照明子系统，计量系统以及用于计量测量的照明样本的方法
公开(公告)号：US09080990B2
公开(公告)日：2015-07-14
申请号：US13061936
申请日：2009-09-29
申请人： Yung-Ho (Alex) Chuang , Vladimir Levinski , Xuefeng Liu
发明人： Yung-Ho (Alex) Chuang , Vladimir Levinski , Xuefeng Liu
IPC分类号： G01N21/55 , G01N21/95 , G01N21/47
CPC分类号： G01N21/9501 , G01N2021/479
摘要： Illumination subsystems of a metrology system, metrology systems, and methods for illuminating a specimen for metrology measurements are provided. One illumination subsystem includes a light source configured to generate coherent pulses of light and a dispersive element positioned in the path of the coherent pulses of light, which is configured to reduce coherence of the pulses of light by mixing spatial and temporal characteristics of light distribution in the pulses of light. The illumination subsystem also includes an electro-optic modulator positioned in the path of the pulses of light exiting the dispersive element and which is configured to reduce the coherence of the pulses of light by temporally modulating the light distribution in the pulses of light. The illumination subsystem is configured to direct the pulses of light from the electro-optic modulator to a specimen positioned in the metrology system.
摘要翻译：提供了计量系统的照明子系统，计量系统和用于度量测量的照明样本的方法。一个照明子系统包括被配置为产生相干的光脉冲的光源和位于相干脉冲光的路径中的色散元件，该色散元件被配置为通过将光分布的空间和时间特征混合在一起来减小光脉冲的相干性光的脉冲。照明子系统还包括位于离开色散元件的光的脉冲的路径中的电光调制器，其被配置为通过暂时调制光脉冲中的光分布来减小光脉冲的相干性。照明子系统被配置为将来自电光调制器的光的脉冲引导到位于计量系统中的样本。

44. 发明授权

US09059138B2 Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure 有权
标题翻译：具有减小的集电极长度的异质结双极晶体管，制造方法和设计结构
公开(公告)号：US09059138B2
公开(公告)日：2015-06-16
申请号：US13358180
申请日：2012-01-25
申请人： Renata Camillo-Castillo , Zhong-Xiang He , Jeffrey B. Johnson , Qizhi Liu , Xuefeng Liu
发明人： Renata Camillo-Castillo , Zhong-Xiang He , Jeffrey B. Johnson , Qizhi Liu , Xuefeng Liu
IPC分类号： H01L29/737 , G06F17/50 , H01L21/331 , H01L29/417 , H01L29/66 , H01L29/10
CPC分类号： H01L29/417 , H01L29/1004 , H01L29/66242 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.
摘要翻译：提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。收集器触点有利地延伸穿过外部基极层的至少一部分。

45. 发明授权

US08860191B2 On-chip transmission line structures with balanced phase delay 有权
标题翻译：具有平衡相位延迟的片上传输线结构
公开(公告)号：US08860191B2
公开(公告)日：2014-10-14
申请号：US13168512
申请日：2011-06-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L23/66 , H01P1/18 , H01L23/522
CPC分类号： H01L23/5222 , H01L23/5225 , H01L23/66 , H01L2223/6638 , H01L2924/0002 , H01P1/184 , Y10T29/49117 , H01L2924/00
摘要： A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.
摘要翻译：一种传输线路结构，相关设计结构及其相关方法。公开了一种结构，其具有：形成在半导体衬底上的多个布线层; 位于布线层中的一对相邻的第一和第二信号线，其中第一信号线包括形成在第一布线层上的第一部分和形成在第二布线层上的第二部分; 第一介电结构，其具有位于第一部分和接地屏蔽之间的第一介电常数; 以及具有不同于所述第一介电常数的第二介电常数的次级介电结构，所述第二介电结构位于所述第二部分和所述接地屏蔽之间，并且所述第二电介质层与所述第二部分共面延伸并且具有长度为基本上与第二部分相同。

46. 发明申请

US20130309681A1 Immortalization of Epithelial Cells and Methods of Use 有权
公开(公告)号：US20130309681A1
公开(公告)日：2013-11-21
申请号：US13885078
申请日：2011-11-11
申请人： Richard Schlegel , Xuefeng Liu
发明人： Richard Schlegel , Xuefeng Liu
IPC分类号： C12N5/071
CPC分类号： C12N5/0683 , C12N5/0625 , C12N5/0631 , C12N5/067 , C12N5/0688 , C12N2500/05 , C12N2500/40 , C12N2501/01 , C12N2501/11 , C12N2501/33 , C12N2501/39 , C12N2501/727 , C12N2502/13 , C12N2502/1323 , C12N2503/02 , C12N2510/04 , C12Q1/6883 , C12Q2600/106 , C12Q2600/158 , G01N33/5091
摘要： The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.

47. 发明授权

US08566759B2 Structure for on chip shielding structure for integrated circuits or devices on a substrate 有权
标题翻译：用于集成电路或基板上的器件的片上屏蔽结构的结构
公开(公告)号：US08566759B2
公开(公告)日：2013-10-22
申请号：US12046750
申请日：2008-03-12
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： G06F17/50
CPC分类号： G01R1/18 , G01R31/2851 , H01L23/552 , H01L23/66 , H01L2223/6627 , H01L2223/665 , H01L2924/0002 , H01L2924/1903 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构包括：围绕和容纳布置在基板上的电路或电路装置的导电结构以及与导电结构相关联的至少一个馈电电容器和一个传输线，并将电源和信号提供给电路或电路装置分别。该设计结构还包括围绕设置在基板上的电路或电路装置的屏蔽结构以及布置在屏蔽结构侧的电容器或传输线的至少一个馈电。

48. 发明申请

US20120323356A1 METHOD OF OPTIMIZING AN OPTICAL PARAMETRIC MODEL FOR STRUCTURAL ANALYSIS USING OPTICAL CRITICAL DIMENSION (OCD) METROLOGY 有权
标题翻译：使用光学关键尺寸（OCD）方法优化结构分析的光学参数模型的方法
公开(公告)号：US20120323356A1
公开(公告)日：2012-12-20
申请号：US13164398
申请日：2011-06-20
申请人： Thaddeus G. Dziura , Yung-Ho Chuang , Bin-Ming Benjamin Tsai , Xuefeng Liu , John J. Hench
发明人： Thaddeus G. Dziura , Yung-Ho Chuang , Bin-Ming Benjamin Tsai , Xuefeng Liu , John J. Hench
IPC分类号： G06F19/00 , G06F17/50
CPC分类号： G01B11/24 , G01B2210/56 , G01N21/47 , G01N21/956 , G01N2021/95615 , G03F7/70625 , G06F17/5009
摘要： Optimization of optical parametric models for structural analysis using optical critical dimension metrology is described. A method includes determining a first optical model fit for a parameter of a structure. The first optical model fit is based on a domain of quantities for a first model of the structure. A first near optical field response is determined for a first quantity of the domain of quantities and a second near optical field response is determined for a second, different quantity of the domain of quantities. The first and second near optical field responses are compared to locate a common region of high optical field intensity for the parameter of the structure. The first model of the structure is modified to provide a second, different model of the structure. A second, different optical model fit is determined for the parameter of the structure based on the second model of the structure.
摘要翻译：描述了使用光学关键尺寸度量结构分析的光学参数模型的优化。一种方法包括确定适合结构参数的第一光学模型。第一个光学模型拟合是基于结构的第一个模型的数量域。对于第一量的量域确定第一近场光响应，并且针对量的第二个不同数量的量确定第二近场光响应。比较第一和第二近场光响应，以定位用于结构参数的高光场强度的公共区域。该结构的第一个模型被修改以提供第二个不同的结构模型。基于结构的第二个模型，确定结构参数的第二个不同的光学模型拟合。

49. 发明授权

US08232920B2 Integrated millimeter wave antenna and transceiver on a substrate 有权
标题翻译：集成毫米波天线和收发器在基板上
公开(公告)号：US08232920B2
公开(公告)日：2012-07-31
申请号：US12187442
申请日：2008-08-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
IPC分类号： H01Q1/38 , H01Q1/40
CPC分类号： H01Q1/2283 , H01Q1/40 , H01Q9/26 , H01Q9/285 , H01Q19/108 , H01Q19/30
摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.
摘要翻译：提供集成收发器，天线和接收器的半导体芯片。收发器位于半导体衬底的前侧。通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。连接到收发器的天线位于位于基板正面的电介质层中。反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。

50. 发明授权

US08120110B2 Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate 有权
标题翻译：在SOI衬底上包括高性能FET和高电压FET的半导体结构
公开(公告)号：US08120110B2
公开(公告)日：2012-02-21
申请号：US12188381
申请日：2008-08-08
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

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