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41. 发明授权

US09026744B2 Enforcing strongly-ordered requests in a weakly-ordered processing 有权
标题翻译：在弱有序的处理中执行强有序的请求
公开(公告)号：US09026744B2
公开(公告)日：2015-05-05
申请号：US11253307
申请日：2005-10-19
申请人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
发明人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译：本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。处理系统包括多个存储器件和多个处理器。每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

42. 发明授权

US08938602B2 Multiple sets of attribute fields within a single page table entry 有权
标题翻译：单个页表条目中的多组属性字段
公开(公告)号：US08938602B2
公开(公告)日：2015-01-20
申请号：US13565434
申请日：2012-08-02
申请人： Colin Christopher Sharp , Thomas Andrew Sartorius
发明人： Colin Christopher Sharp , Thomas Andrew Sartorius
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/1009 , G06F12/145 , G06F2212/656 , Y02D10/13
摘要： A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.
摘要翻译：第一处理单元和第二处理单元可以访问存储第一处理单元和第二处理单元共用的公共页表的系统存储器。公共页表可以将虚拟内存地址存储到由应用程序的作业访问的存储块的物理内存地址映射。公共页表内的页条目可以包括第一组属性位，其定义第一处理单元对存储块的可访问性;第二组属性位，其定义第二处理单元的相同存储块的可访问性，以及定义存储块的物理地址的物理地址位。

43. 发明授权

US08924685B2 Configuring surrogate memory accessing agents using non-priviledged processes 有权
标题翻译：使用非授权进程配置代理内存访问代理
公开(公告)号：US08924685B2
公开(公告)日：2014-12-30
申请号：US12777324
申请日：2010-05-11
申请人： Thomas Andrew Sartorius
发明人： Thomas Andrew Sartorius
IPC分类号： G06F12/10 , G06F9/34 , G06F9/35
CPC分类号： G06F9/34 , G06F9/35 , G06F12/1027 , G06F12/1081 , Y02D10/13
摘要： Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address.
摘要翻译：描述使用用于翻译和存储数据值的指令来配置代理存储器访问代理。在一个实施例中，接收包括指定要转换的数据值的第一操作数和指定与其中存储数据值的代理存储器访问代理寄存器的位置相关联的虚拟地址的第二操作数的指令。数据值可以转换为第一个物理地址。虚拟地址可以转换为第二个物理地址。第一物理地址基于第二物理地址存储在代理存储器访问代理寄存器中。

44. 发明申请

US20140040593A1 MULTIPLE SETS OF ATTRIBUTE FIELDS WITHIN A SINGLE PAGE TABLE ENTRY 有权
标题翻译：在单页表中多个属性集合
公开(公告)号：US20140040593A1
公开(公告)日：2014-02-06
申请号：US13565434
申请日：2012-08-02
申请人： Colin Christopher Sharp , Thomas Andrew Sartorius
发明人： Colin Christopher Sharp , Thomas Andrew Sartorius
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/145 , G06F2212/656 , Y02D10/13
摘要： A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.
摘要翻译：第一处理单元和第二处理单元可以访问存储第一处理单元和第二处理单元共用的公共页表的系统存储器。公共页表可以将虚拟内存地址存储到由应用程序的作业访问的存储块的物理内存地址映射。公共页表内的页条目可以包括第一组属性位，其定义第一处理单元对存储块的可访问性;第二组属性位，其定义第二处理单元的相同存储块的可访问性，以及定义存储块的物理地址的物理地址位。

45. 发明申请

US20120226888A1 Memory Management Unit With Pre-Filling Capability 有权
标题翻译：具有预填充能力的内存管理单元
公开(公告)号：US20120226888A1
公开(公告)日：2012-09-06
申请号：US13371506
申请日：2012-02-13
申请人： Bohuslav Rychlik , Thomas Andrew Sartorius , Michael William Morrow , Raymond P. Palma
发明人： Bohuslav Rychlik , Thomas Andrew Sartorius , Michael William Morrow , Raymond P. Palma
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/6026 , G06F2212/6028 , G06F2212/654
摘要： Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.
摘要翻译：用于内存管理单元（MMU）的系统和方法被配置为自动预先填充具有将要使用的地址转换条目的翻译后备缓冲器（TLB），从而减少TLB未命中率并提高性能。可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。预测可以从外部设备导出，或者基于步幅值，其中步幅值可以是预定常数，或者基于访问模式动态地改变。预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。

46. 发明授权

US08239657B2 Address translation method and apparatus 有权
标题翻译：地址转换方法和装置
公开(公告)号：US08239657B2
公开(公告)日：2012-08-07
申请号：US11672066
申请日：2007-02-07
申请人： Brian Joseph Kopec , Victor Roberts Augsburg , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Brian Joseph Kopec , Victor Roberts Augsburg , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F12/04
CPC分类号： G06F12/04 , G06F12/1027 , G06F2212/655 , Y02D10/13
摘要： Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.
摘要翻译：通过识别导致存储器中的不同页面之间的边界交叉的地址以及链接与两个存储器页面相关联的地址转换信息来改进处理器内的地址转换性能。根据处理器的一个实施例，处理器包括被配置为识别对跨越第一和第二存储器页之间的页边界的存储区的访问的电路。电路还被配置为链接与第一和第二存储器页相关联的地址转换信息。因此，响应于后续访问相同的存储器区域，可以基于单个地址转换来检索与第一和第二存储器页面相关联的地址转换信息。

47. 发明授权

US08078803B2 Apparatus and methods to reduce castouts in a multi-level cache hierarchy 有权
标题翻译：减少多级缓存层次结构中的丢弃的装置和方法
公开(公告)号：US08078803B2
公开(公告)日：2011-12-13
申请号：US11669245
申请日：2007-01-31
申请人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
摘要翻译：技术和方法用于控制从较低级别缓存中移位的高速缓存行的更高级缓存的分配。对于被确定为在下一级高速缓存中是冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而控制转储。为此，选择在下一级缓存中移位的行。识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。

48. 发明授权

US07917731B2 Method and apparatus for prefetching non-sequential instruction addresses 有权
标题翻译：用于预取非顺序指令地址的方法和装置
公开(公告)号：US07917731B2
公开(公告)日：2011-03-29
申请号：US11461883
申请日：2006-08-02
申请人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/32
CPC分类号： G06F9/3804 , G06F9/3806
摘要： A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.
摘要翻译：处理器对非顺序指令地址执行预取操作。如果第一指令地址在指令高速缓存中丢失并且作为获取操作的一部分访问高阶存储器，并且检测并预测与第一指令地址或第一指令地址之后的地址相关联的分支指令，则预取在高级存储器访问期间使用预测的分支目标地址执行操作。如果预取分支目标地址在预取操作期间在指令高速缓存中命中，则不检索相关联的指令以节省功率。如果在预取操作期间预测的分支目标地址在指令高速缓存中丢失，则可以使用预测的分支指令地址来启动高阶存储器访问。在任一种情况下，第一指令地址被重新加载到提取级流水线中以等待指令从其高阶存储器访问返回。

49. 发明授权

US07725684B2 Speculative instruction issue in a simultaneously multithreaded processor 有权
标题翻译：同时多线程处理器中的推测性指令问题
公开(公告)号：US07725684B2
公开(公告)日：2010-05-25
申请号：US12105091
申请日：2008-04-17
申请人： Victor R. Augsburg , Jeffrey T. Bridges , Michael S. Mcilvaine , Thomas Andrew Sartorius , Rodney W. Smith
发明人： Victor R. Augsburg , Jeffrey T. Bridges , Michael S. Mcilvaine , Thomas Andrew Sartorius , Rodney W. Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3826 , G06F9/3851
摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.
摘要翻译：一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。指令问题逻辑根据当指令到达要求管道中的阶段时所需操作数将可用的概率推测性地发出给定线程的指令。如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。

50. 发明申请

US20080229069A1 System, Method And Software To Preload Instructions From An Instruction Set Other Than One Currently Executing 有权
标题翻译：系统，方法和软件可以从目前正在执行的指令集预加载指令
公开(公告)号：US20080229069A1
公开(公告)日：2008-09-18
申请号：US11685850
申请日：2007-03-14
申请人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/44 , G06F9/30
CPC分类号： G06F9/30196 , G06F9/30047 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI may be set prior to executing the preload instruction, or may comprise part of the preload instruction or the preload target address.
摘要翻译：在第一处理器指令集操作模式中执行的指令预加载指令可操作以在不同的第二指令集中正确地预加载指令。根据指令集预加载指示符（ISPI），根据第二指令集编码对指令进行预解码。在各种实施例中，可以在执行预加载指令之前设置ISPI，或者可以包括预加载指令或预加载目标地址的一部分。

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