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41. 发明授权

US5452426A Coordinating speculative and committed state register source data and immediate source data in a processor 失效
标题翻译：在处理器中协调推测和提交的状态寄存器源数据和即时源数据
公开(公告)号：US5452426A
公开(公告)日：1995-09-19
申请号：US177240
申请日：1994-01-04
申请人： David B. Papworth , Glenn J. Hinton , Michael A. Fetterman , Robert P. Colwell , Andrew F. Glew
发明人： David B. Papworth , Glenn J. Hinton , Michael A. Fetterman , Robert P. Colwell , Andrew F. Glew
IPC分类号： G06F9/38 , G06F9/24 , G06F9/28
CPC分类号： G06F9/30167 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857
摘要： A mechanism for coordinating source data in a processor, wherein a decode circuit issues instructions comprising at least one immediate valid flag and at least one logical register source. The immediate valid flag indicates whether an immediate operand for the instruction is available on an immediate data bus, and the logical register source specifies a physical register or a committed state register. A speculative result data value and a speculative source valid flag are read from the physical register, and a committed result data value is read from the committed state register. The speculative result data value and the speculative source valid flag or the committed result data value and the committed source valid flag provide a source data value and a source data valid flag for scheduling an execution of the instruction.
摘要翻译：一种用于在处理器中协调源数据的机制，其中解码电路发出包括至少一个即时有效标志和至少一个逻辑寄存器源的指令。即时有效标志指示在立即数据总线上是否有指令的立即操作数可用，逻辑寄存器源指定物理寄存器或提交状态寄存器。从物理寄存器读取推测结果数据值和推测源有效标志，并从承诺状态寄存器读取提交结果数据值。推测结果数据值和推测源有效标志或提交结果数据值和提交的源有效标志提供源数据值和源数据有效标志，用于调度指令的执行。

42. 发明授权

US5987600A Exception handling in a processor that performs speculative out-of-order instruction execution 失效
标题翻译：处理器中执行异常指令执行的异常处理
公开(公告)号：US5987600A
公开(公告)日：1999-11-16
申请号：US851140
申请日：1997-05-05
申请人： David B. Papworth , Glenn J. Hinton , Michael A. Fetterman , Robert P. Colwell , Andrew F. Glew
发明人： David B. Papworth , Glenn J. Hinton , Michael A. Fetterman , Robert P. Colwell , Andrew F. Glew
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3865 , G06F9/3842 , G06F9/3863
摘要： A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.
摘要翻译：用于协调处理器中的异常的方法和电路。处理器为每个指令生成结果数据值和异常数据值，其中异常数据值指定相应指令是否引起异常。处理器以顺序程序顺序将结果数据值提交给处理器的架构状态，并且如果异常由异常数据值之一指示，则提取异常处理程序来处理异常。如果在结果数据值提交到处理器的架构状态时检测到异步事件，处理器将获取异步事件处理程序来处理异步事件。

43. 发明授权

US5627985A Speculative and committed resource files in an out-of-order processor 失效
标题翻译：乱序处理器中的投机和承诺资源文件
公开(公告)号：US5627985A
公开(公告)日：1997-05-06
申请号：US177244
申请日：1994-01-04
申请人： Michael A. Fetterman , Andrew F. Glew , David B. Papworth , Glenn J. Hinton , Robert P. Colwell
发明人： Michael A. Fetterman , Andrew F. Glew , David B. Papworth , Glenn J. Hinton , Robert P. Colwell
IPC分类号： G06F9/38 , G06F9/34
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.
摘要翻译：一种推测执行乱序处理器，包括一个包含多个物理寄存器的重排序电路，该多个物理寄存器缓冲整数和浮点运算的推测执行结果，以及一个包含多个提交状态寄存器的实际寄存器电路，该寄存器电路缓冲任一整数的提交执行结果或浮点运算，具体取决于寄存器。重排序和实际寄存器电路读取输入微操作的推测和确定的源数据值，并通过公共数据路径将推测和承诺的源数据值传输到微操作调度电路。退出逻辑电路通过将推测执行结果从重新排序电路传送到实际寄存器电路来将推测执行结果提交到架构状态。

44. 发明授权

US5604878A Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path 失效
标题翻译：避免共享共同回写路径的执行单元之间的回写冲突的方法和装置
公开(公告)号：US5604878A
公开(公告)日：1997-02-18
申请号：US513679
申请日：1995-08-01
申请人： Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Robert W. Martell , David B. Papworth
发明人： Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Robert W. Martell , David B. Papworth
IPC分类号： G06F9/38 , G06F13/00
CPC分类号： G06F9/3873 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.
摘要翻译：执行可能参与回写冲突的功能单位的管道延长，以避免冲突。提供逻辑电路用于比较两个并发执行的执行单元管线的深度，以确定冲突是否会发展。当看来两个执行单元将尝试同时回写时，将指示具有较短流水线的执行单元向其流水线添加一个阶段，将其结果存储在一个时钟周期的延迟缓冲器中。冲突解决后，延长给定功能单位管道的指示将被撤销。多级执行单元被设计为用信号通知保留站来延迟各种指令的发送以避免执行单元之间的冲突。

45. 发明授权

US5854914A Mechanism to improved execution of misaligned loads 失效
标题翻译：改善不正确负载执行的机制
公开(公告)号：US5854914A
公开(公告)日：1998-12-29
申请号：US711096
申请日：1996-09-10
申请人： Milind Bodas , Glenn J. Hinton , Andrew F. Glew
发明人： Milind Bodas , Glenn J. Hinton , Andrew F. Glew
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3816 , G06F9/3834 , G06F9/3842
摘要： A method and apparatus for executing a misaligned load. The method begins with receiving a load request to load data from a first memory location. An entry in a store buffer is tested to determine whether the entry corresponds to the first memory location. The entry is also tested to determine whether the entry corresponds to a second memory location subsequent to the first memory location. The load request is blocked if the entry corresponds to the first memory location or the second memory location. After a store operation for the store buffer entry is executed, the load request may be unblocked. The apparatus is a processor or a computer system comprising a load buffer capable of storing a load request address in response to a load request. The processor includes an incrementing circuit that generates an incremented load request address. The processor also includes a store buffer containing a portion of a store request address. The store buffer includes comparison circuitry that compares the portion of the store request address to the load request and the incremented load request address, and generates a blocking signal if the either of the load request address and the incremented load request correspond to the store request address.
摘要翻译：一种用于执行不对中负载的方法和装置。该方法从接收到从第一存储器位置加载数据的加载请求开始。测试存储缓冲区中的条目以确定条目是否对应于第一存储器位置。还测试该条目以确定条目是否对应于第一存储器位置之后的第二存储器位置。如果条目对应于第一个存储器位置或第二个存储器位置，则加载请求被阻止。在执行存储缓冲器条目的存储操作之后，加载请求可以被解除阻塞。该装置是包括能够响应于负载请求而存储加载请求地址的加载缓冲器的处理器或计算机系统。处理器包括生成递增的加载请求地址的递增电路。该处理器还包括一个包含存储请求地址的一部分的存储缓冲器。存储缓冲器包括比较电路，其将存储请求地址的部分与加载请求和增加的加载请求地址进行比较，并且如果加载请求地址和增加的加载请求中的任一个对应于存储请求地址，则产生阻塞信号。

46. 发明授权

US06047369A Flag renaming and flag masks within register alias table 失效
标题翻译：标志在注册表别名中重命名和标记掩码
公开(公告)号：US06047369A
公开(公告)日：2000-04-04
申请号：US204521
申请日：1994-02-28
申请人： Robert P. Colwell , Andrew F. Glew , Atiq A. Bajwa , Glenn J. Hinton , Michael A. Fetterman
发明人： Robert P. Colwell , Andrew F. Glew , Atiq A. Bajwa , Glenn J. Hinton , Michael A. Fetterman
IPC分类号： G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/3013 , G06F9/30134 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, the flags used by these instructions are renamed. In general, a RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies between instructions that reduce overall superscalar processing performance for the microprocessor. The renamed flag registers contain several flag bits and various flag bits may be updated or read by different instructions. Also, static and dynamic flag masks are associated with particular instructions and indicate which flags are capable of being updated by a particular instruction and also indicate which flags are actually updated by the instruction. Static flag masks are used in flag renaming and dynamic flag masks are used at retirement. The invention also discovers cases in which a flag register is required that is a superset of the previously renamed flag register portion.
摘要翻译：一种用于重命名寄存器别名表（“RAT”）中的标志以增加处理器并行性并且还提供和使用与各个指令相关联的标志掩码的机制和方法。为了减少并发处理的指令之间的数据依赖性，这些指令使用的标志被重命名。通常，RAT单元提供寄存器重命名以提供比通常在给定宏架构的逻辑寄存器集（例如Intel架构或PowerPC或Alpha设计）内通常可用的更大的物理寄存器集，以消除指令之间的虚假数据依赖性这降低了微处理器的整体超标量处理性能。重命名的标志寄存器包含几个标志位，各种标志位可能被不同的指令更新或读取。此外，静态和动态标志掩码与特定指令相关联，并且指示哪些标志能够被特定指令更新，并且还指示哪些标志实际上被指令更新。在标志重命名中使用静态标志掩码，退休时使用动态标志掩码。本发明还发现需要作为先前重命名的标志寄存器部分的超集的标志寄存器的情况。

47. 发明授权

US5584001A Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history 失效
标题翻译：分支目标缓冲区，用于使用预测的分支历史动态预测分支指令结果
公开(公告)号：US5584001A
公开(公告)日：1996-12-10
申请号：US509331
申请日：1995-07-31
申请人： Bradley D. Hoyt , Glenn J. Hinton , Andrew F. Glew , Subramanian Natarajan
发明人： Bradley D. Hoyt , Glenn J. Hinton , Andrew F. Glew , Subramanian Natarajan
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A branch prediction mechanism that maintains both speculative history and actual history for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history plus the "history" of recent branch predictions for the branch. If the speculative branch history contains any recent predictions, then a speculation bit is set. When the speculation bit is set, this indicates that there is speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a misprediction is made for the branch, the speculation bit is cleared since the speculative history contains inaccurate branch history.
摘要翻译：分支预测机制，保持分支目标缓冲区中每个分支指令的推测历史和实际历史。实际的分支历史包含分支指令的完全解决事件的分支历史。投机分支历史包含实际历史加上分支机构最近分支预测的“历史”。如果推测分支历史记录包含任何最近的预测，则设置推测位。当猜测位置位时，表示有一个分支的推测历史。因此，当设置推测位时，推测历史用于进行分支预测。如果对分行进行错误预测，则推测位将被清除，因为投机历史记录包含不准确的分支历史记录。

48. 发明授权

US5751996A Method and apparatus for processing memory-type information within a microprocessor 失效
标题翻译：用于处理微处理器内的存储器类型信息的方法和装置
公开(公告)号：US5751996A
公开(公告)日：1998-05-12
申请号：US767799
申请日：1996-12-17
申请人： Andrew F. Glew , Glenn J. Hinton
发明人： Andrew F. Glew , Glenn J. Hinton
IPC分类号： G06F9/312 , G06F9/38 , G06F12/08
CPC分类号： G06F9/30043 , G06F12/0804 , G06F12/0888 , G06F9/3824 , G06F9/3842 , G06F9/3857
摘要： A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor. Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed in accordance with any one of a number of processing protocols including write-through processing, write-back processing, write-protect processing, restricted-cacheability processing, uncacheable speculatable write-combining processing, or uncacheable processing. By providing memory-type information explicitly within the microprocessor, the type of memory identified by a micro-instruction is known before the micro-instruction is processed. Accordingly, the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. For example, if the memory location identified by the micro-instruction is known to be uncacheable, a data cache unit is bypassed and external memory is accessed directly. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor capable of generating speculative memory micro-instruction. Also, the microprocessor may be only one of a number of microprocessors within a multiprocessor system.
摘要翻译：识别包含有存储器位置范围的存储器类型的存储器类型值被明确地存储在微处理器内。在处理诸如加载或存储之类的存储器微指令之前，为由存储器微指令识别的存储器位置确定存储器类型。一旦已知存储器类型，存储器微指令根据多种处理协议中的任何一种被处理，包括直写处理，回写处理，写保护处理，限制高速缓存处理，不可缓存的可写入写入 - 组合处理或不可缓解的处理。通过在微处理器内显式提供存储器类型信息，在微指令被处理之前，已经知道由微指令识别的存储器类型。因此，处理微指令的协议可以有效地针对存储器类型进行定制。例如，如果由微指令识别的存储器位置已知是不可缓存的，则旁路数据高速缓存单元，并直接访问外部存储器。在示例性实施例中，微处理器是能够产生推测存储器微指令的无序微处理器。此外，微处理器可能只是多处理器系统内的多个微处理器之一。

49. 发明授权

US5903751A Method and apparatus for implementing a branch target buffer in CISC processor 失效
标题翻译：在CISC处理器中实现分支目标缓冲器的方法和装置
公开(公告)号：US5903751A
公开(公告)日：1999-05-11
申请号：US931807
申请日：1997-09-16
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.
摘要翻译：公开了一种使用计算机指令流预测分支指令的计算机处理器中的分支目标缓冲器电路。分支目标缓冲器电路使用分支目标缓冲器高速缓存，其存储关于先前执行的分支指令的分支信息。存储在分支目标缓冲区高速缓存中的分支信息由每个分支指令的最后一个字节寻址。当计算机处理器中的指令获取单元获取指令块时，它向分支目标缓冲器电路发送指令指针。基于指令指针，分支目标缓冲器电路查找分支目标缓冲区高速缓存以查看正在获取的块中的任何指令是否是分支指令。当分支目标缓冲器电路在分支目标缓冲器高速缓存中找到即将到来的分支指令时，分支目标缓冲器电路通知指令获取单元关于即将到来的分支指令。

50. 发明授权

US5586278A Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor 失效
标题翻译：在无序微处理器中的分支错误预测之后状态恢复的方法和装置
公开(公告)号：US5586278A
公开(公告)日：1996-12-17
申请号：US639244
申请日：1996-04-22
申请人： David B. Papworth , Glenn J. Hinton
发明人： David B. Papworth , Glenn J. Hinton
IPC分类号： G06F9/38
CPC分类号： G06F9/3863
摘要： A method of state recovery following a branch misprediction or an undetected branch instruction. If, during execution of a branch instruction in an out-of-order unit, it is determined that the branch has been mispredicted, or if a taken branch has not been detected, then a JEClear signal is asserted to flush the instruction fetch unit and decoder section, and to change the instruction pointer to the actual target address. Within the out-of-order section, the instructions preceding the branch instruction are allowed to continue execution and proceed to in-order retirement. Simultaneously, instructions fetched at the actual target address are decoded, but not allowed to issue therefrom until the branch instruction has been retired from the out-of-order section, after which all instructions within the out-of-order section are flushed, and then decoded instructions are allowed to issue from the decoder. The state recovery method advantageously provides efficient utilization of processor time.
摘要翻译：分支错误预测或未检测到的分支指令之后的状态恢复方法。如果在执行无序单元中的分支指令时，确定分支已经被错误预测，或者如果未被检测到被采取的分支，则断言JEClear信号以刷新指令获取单元，并且解码器部分，并将指令指针更改为实际目标地址。在无序部分中，分支指令之前的指令被允许继续执行，并进行到订单退休。同时，在实际目标地址处获取的指令被解码，但是在分支指令已经从无序部分退出之前不允许发出指令，之后清除无序部分内的所有指令，以及则解码指令被允许从解码器发出。状态恢复方法有利地提供了处理器时间的有效利用。

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