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41. 发明申请

US20110119211A1 SYSTEM AND METHOD FOR ASSESSING RISK 有权
标题翻译：用于评估风险的系统和方法
公开(公告)号：US20110119211A1
公开(公告)日：2011-05-19
申请号：US12694243
申请日：2010-01-26
申请人： William Michael Lay , Yi Wu , Fan Tao Pu , Alain Kouyaté
发明人： William Michael Lay , Yi Wu , Fan Tao Pu , Alain Kouyaté
IPC分类号： G06F15/18 , G06F17/00
CPC分类号： G06N5/02 , G06Q10/0635 , G06Q20/4016
摘要： The invention describes systems and methods of assessing risk using a computer. A computer-based system including an enrollment module, a data aggregation module, a risk assessment module, and a memory is provided for assessing risks. The enrollment receives, at a computer, personal information regarding at least one entity. The data aggregation module receives, at the computer, risk information regarding the entity according to the personal information from at least one data source. The risk assessment module converts the risk information to assessment information. The memory stores the personal information, the risk information, and/or the assessment information on the computer.
摘要翻译：本发明描述了使用计算机评估风险的系统和方法。提供了一种基于计算机的系统，包括注册模块，数据聚合模块，风险评估模块和内存，用于评估风险。注册在计算机上接收关于至少一个实体的个人信息。数据聚合模块在计算机处接收来自至少一个数据源的根据个人信息的关于实体的风险信息。风险评估模块将风险信息转换为评估信息。存储器将个人信息，风险信息和/或评估信息存储在计算机上。

42. 发明授权

US07917878B1 Method for place and route of multicore chip 有权
标题翻译：多核芯片的放置和路由方法
公开(公告)号：US07917878B1
公开(公告)日：2011-03-29
申请号：US12022950
申请日：2008-01-30
申请人： Dajen Huang , Yi Wu , Robert R. Brown
发明人： Dajen Huang , Yi Wu , Robert R. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A number of virtual regionalization lines are laid out across a chip such that the virtual regionalization lines delineate a plurality of regions on the chip. One of the plurality of regions on the chip is designated as a master region and each of a remainder of the plurality of regions on the chip is designated as a duplicate region. A number of functional blocks are placed in the master region. Each of the functional blocks is replicated in each duplicate region by placing each functional block in each duplicate region so as to be symmetric with the corresponding functional block in the master region about the virtual regionalization lines. Wires are routed in the master region. The wires routed in the master region are replicated in each duplicate region so as to be symmetric about the virtual regionalization lines.
摘要翻译：跨芯片布置了多个虚拟区域化线，使得虚拟区域化线描绘了芯片上的多个区域。芯片上的多个区域中的一个被指定为主区域，并且芯片上的多个区域的其余部分中的每一个被指定为重复区域。主区域中放置了多个功能块。通过将每个功能块放置在每个重复区域中以与主区域中的相应功能块对称，关于虚拟区域化线，每个功能块被复制在每个重复区域中。电线在主区域中路由。在主区域中路由的电线被复制在每个重复区域中，以便关于虚拟区域化线对称。

43. 发明申请

US20100325600A1 ROUTING NETS OVER CIRCUIT BLOCKS IN A HIERARCHICAL CIRCUIT DESIGN 有权
标题翻译：在分层电路设计中通过电路块布线网络
公开(公告)号：US20100325600A1
公开(公告)日：2010-12-23
申请号：US12490023
申请日：2009-06-23
申请人： Yi Wu , Dajen Huang , Kalon S. Holdbrook
发明人： Yi Wu , Dajen Huang , Kalon S. Holdbrook
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Some embodiments of the present invention provide a system that routes nets over circuit blocks in a hierarchical circuit design. During operation, the system can receive a set of circuit blocks. At least some terminals of the circuit blocks may be desired to be electrically linked together using a net which is expected to be routed over one or more circuit blocks. The system may divide an area associated with a block (e.g., an area in a metal layer which is situated above the block) into a set of tiles. Next, the system may assign costs to at least some of the tiles in the set of tiles. The system can then use the costs during routing. Note that using the costs of the tiles during routing makes it more likely that buffers can be used wherever required to meet slew and timing requirements.
摘要翻译：本发明的一些实施例提供一种在分层电路设计中将网络路由到电路块上的系统。在运行期间，系统可以接收一组电路块。电路块的至少一些端子可能期望使用期望在一个或多个电路块上布线的网电连接在一起。系统可以将与块（例如，位于块之上的金属层中的区域）相关联的区域划分成一组瓦片。接下来，系统可以将成本分配给该组瓦片中的至少一些瓦片。然后，系统可以在路由期间使用成本。请注意，在路由期间使用瓦片的成本使得缓冲区更有可能在需要满足压缩和时序要求的地方使用。

44. 发明申请

US20100128760A1 METHODS, COMPUTER-READABLE MEDIA AND COMPUTER-IMPLEMENTED TOOLS FOR PRE-ROUTE REPEATER INSERTION 有权
标题翻译：方法，计算机可读介质和计算机实现的前路由器插入工具
公开(公告)号：US20100128760A1
公开(公告)日：2010-05-27
申请号：US12324439
申请日：2008-11-26
申请人： James G. Ballard , Yi Wu
发明人： James G. Ballard , Yi Wu
IPC分类号： H03K11/00
CPC分类号： G06F17/5077
摘要： A method of performing a pre-route repeater insertion methodology for at least part of a circuit design may include: partitioning at least part of a circuit design into a plurality of tiles; determining at least one attribute of individual tiles of the plurality of tiles; and determining a repeater solution based at least in part on the determined attributes of the individual tiles. A computer implemented tool for performing a pre-route repeater insertion methodology for at least part of a circuit design may include: a module configured to partition at least part of a circuit design into a plurality of tiles; a module configured to determine at least one attribute of individual tiles of the plurality of tiles; and a module configured to determine a repeater solution based at least in part on the determined attributes of the individual tiles.
摘要翻译：执行电路设计的至少一部分的前路由中继器插入方法的方法可以包括：将电路设计的至少一部分划分成多个瓦片; 确定所述多个瓦片中的各个瓦片的至少一个属性; 以及至少部分地基于所确定的各个瓦片的属性来确定中继器解决方案。用于对电路设计的至少一部分执行预路由中继器插入方法的计算机实现工具可以包括：被配置为将电路设计的至少一部分划分成多个瓦片的模块; 模块，被配置为确定所述多个瓦片中的各个瓦片的至少一个属性; 以及模块，被配置为至少部分地基于所确定的各个瓦片的属性来确定中继器解决方案。

45. 发明申请

US20090232160A1 Bandwidth Requests of Scheduling Services 审中-公开
标题翻译：调度服务的带宽请求
公开(公告)号：US20090232160A1
公开(公告)日：2009-09-17
申请号：US12171170
申请日：2008-07-10
申请人： Yi Wu , Yan Qun Le , Dong Mei Zhang
发明人： Yi Wu , Yan Qun Le , Dong Mei Zhang
IPC分类号： H04J3/16
CPC分类号： H04W72/1284
摘要： Methods and apparatus for providing bandwidth requests of scheduling services, such as, for example, best effort services, in a telecommunication network are disclosed. An example method includes receiving a plurality of bandwidth requests from different scheduling connections. The example method further includes combining the plurality of bandwidth requests in a common bandwidth request.
摘要翻译：公开了用于在电信网络中提供调度服务的带宽请求（例如，尽力服务）的方法和装置。示例性方法包括从不同的调度连接接收多个带宽请求。该示例方法还包括在公共带宽请求中组合多个带宽请求。

46. 发明申请

US20090214560A1 BINDING MOLECULES TO THE HUMAN OX40 RECEPTOR 有权
标题翻译：结合人类OX40受体的分子
公开(公告)号：US20090214560A1
公开(公告)日：2009-08-27
申请号：US12332944
申请日：2008-12-11
申请人： Jing Min , Yanli Wu , Rory F. Finn , Barrett R. Thiele , Wei Liao , Ronald P. Gladue , Arvind Rajpal , Timothy J. Paradis , Peter Brams , Brigitte Devaux , Yi Wu , Kristopher Toy , Heidi N. LeBlanc , Haichun Huang
发明人： Jing Min , Yanli Wu , Rory F. Finn , Barrett R. Thiele , Wei Liao , Ronald P. Gladue , Arvind Rajpal , Timothy J. Paradis , Peter Brams , Brigitte Devaux , Yi Wu , Kristopher Toy , Heidi N. LeBlanc , Haichun Huang
IPC分类号： A61K39/395 , C07K16/18 , C12N15/11 , C12N15/00 , C12N5/06
CPC分类号： C07K16/2878 , A61K2039/505 , C07K2317/14 , C07K2317/21 , C07K2317/565 , C07K2317/92
摘要： The present disclosure provides isolated binding molecules that bind to the human OX40R, nucleic acid molecules encoding an amino acid sequence of the binding molecules vectors comprising the nucleic acid molecules, host cells containing the vectors, methods of making the binding molecules, pharmaceutical compositions containing the binding molecules, and methods of using the binding molecules or compositions.
摘要翻译：本公开提供了结合人OX40R的分离的结合分子，编码结合分子的氨基酸序列的核酸分子，包含核酸分子的载体，含有载体的宿主细胞，制备结合分子的方法，含有结合分子，以及使用结合分子或组合物的方法。

47. 发明授权

US07577933B1 Timing driven pin assignment 有权
标题翻译：定时驱动引脚分配
公开(公告)号：US07577933B1
公开(公告)日：2009-08-18
申请号：US11601148
申请日：2006-11-17
申请人： Yi Wu , Kenan Yu , James G. Ballard
发明人： Yi Wu , Kenan Yu , James G. Ballard
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design information includes a floorplan that sets forth an arrangement of blocks in the integrated circuit and timing information for interconnections between the blocks. Based on the timing information, routing information is determined for the interconnections between the blocks. The routing information includes physical routes and physical pin placements for the interconnections.
摘要翻译：公开了用于确定集成电路中的引脚分配的机制。更具体地，该机制涉及访问集成电路的设计信息。设计信息包括阐述集成电路中的块的布置的布局图和用于块之间的互连的定时信息。基于定时信息，确定块之间的互连的路由信息。路由信息包括互连的物理路由和物理引脚放置。

48. 发明授权

US07519933B2 Converging repeater methodology for channel-limited SOC microprocessors 有权
标题翻译：用于通道限制SOC微处理器的汇聚中继器方法
公开(公告)号：US07519933B2
公开(公告)日：2009-04-14
申请号：US11524820
申请日：2006-09-21
申请人： Arjun Dutt , Dajen Huang , Yi Wu
发明人： Arjun Dutt , Dajen Huang , Yi Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for inserting repeaters in an integrated circuit includes establishing a set of initial constraints for a given set of buses; assigning at least one repeater corresponding to each of the given set of buses based on the set of initial constraints; progressively relaxing the set of initial constraints to form a new set of constraints for a new set of buses and assigning at least one repeater corresponding to each of the new set of buses based on the new set of constraints; and routing assigned repeaters to each of the new set of buses in the integrated circuit.
摘要翻译：一种用于在集成电路中插入中继器的方法包括为给定的一组总线建立一组初始约束; 基于所述初始约束集，分配对应于所述给定总线集合中的每一个的至少一个中继器; 逐渐放松一组初始约束以形成新的一组总线的新的约束集合，并且基于新的约束集合分配对应于每组新的总线的至少一个中继器; 并将分配的中继器路由到集成电路中的每组新的总线。

49. 发明申请

US20080077899A1 Converging repeater methodology for channel-limited SOC microprocessors 有权
标题翻译：用于通道限制SOC微处理器的汇聚中继器方法
公开(公告)号：US20080077899A1
公开(公告)日：2008-03-27
申请号：US11524820
申请日：2006-09-21
申请人： Arjun Dutt , Dajen Huang , Yi Wu
发明人： Arjun Dutt , Dajen Huang , Yi Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for inserting repeaters in an integrated circuit includes establishing a set of initial constraints for a given set of buses; assigning at least one repeater corresponding to each of the given set of buses based on the set of initial constraints; progressively relaxing the set of initial constraints to form a new set of constraints for a new set of buses and assigning at least one repeater corresponding to each of the new set of buses based on the new set of constraints; and routing assigned repeaters to each of the new set of buses in the integrated circuit.
摘要翻译：一种用于在集成电路中插入中继器的方法包括为给定的一组总线建立一组初始约束; 基于所述初始约束集，分配对应于所述给定总线集合中的每一个的至少一个中继器; 逐渐放松一组初始约束以形成新的一组总线的新的约束集合，并且基于新的约束集合分配对应于每组新的总线的至少一个中继器; 并将分配的中继器路由到集成电路中的每组新的总线。

50. 发明申请

US20070286077A1 COMMUNICATION SYSTEM 有权
标题翻译：通讯系统
公开(公告)号：US20070286077A1
公开(公告)日：2007-12-13
申请号：US11740810
申请日：2007-04-26
申请人： Yi Wu
发明人： Yi Wu
IPC分类号： H04L12/26 , H04J3/24
CPC分类号： H04L1/1835 , H04L1/1854
摘要： A method of transmitting data in a communication system. Data packets are transmitted from a first node to a second node on a first channel. An acknowledgement packet is transmitted from the second node to the first node on a second channel in response to receiving a number of packets on the first channel. The number of data packets that the acknowledgment packet is sent in response to is adjustable.
摘要翻译：一种在通信系统中发送数据的方法。数据分组在第一信道上从第一节点发送到第二节点。响应于在第一信道上接收到多个分组，确认分组从第二节点发送到第二信道上的第一节点。响应中发送确认数据包的数据包数量是可调整的。

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