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41. 发明授权

US06178130B1 Apparatus and method for refreshing subsets of memory devices in a memory system 有权
标题翻译：用于刷新存储器系统中存储器件子集的装置和方法
公开(公告)号：US06178130B1
公开(公告)日：2001-01-23
申请号：US09169590
申请日：1998-10-09
申请人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel , Thomas J. Holman , Andrew V. Anderson
发明人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel , Thomas J. Holman , Andrew V. Anderson
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A memory system includes a set of memory devices. An interconnect structure links the set of memory devices to one another. A memory controller is connected to the interconnect structure. The memory controller is configured to apply a control signal to the interconnect structure such that a specified subset of the set of memory devices performs a refresh operation.
摘要翻译：存储器系统包括一组存储器件。互连结构将存储器件集合彼此连接。存储器控制器连接到互连结构。存储器控制器被配置为将控制信号施加到互连结构，使得该组存储器件的指定子集执行刷新操作。

42. 发明授权

US6154821A Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain 失效
标题翻译：通过调整读取域来初始化动态随机存取存储器（DRAM）设备的方法和装置
公开(公告)号：US6154821A
公开(公告)日：2000-11-28
申请号：US38358
申请日：1998-03-10
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G06F13/00
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C7/20 , G11C8/12 , G11C2207/2227 , G11C2207/2254 , Y02B60/1235
摘要： A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.
摘要翻译：提供了用于初始化动态随机存取存储器（DRAM）装置的方法和装置，其中通过确定耦合到总线的多个DRAM装置中的每一个的响应时间来对信道进行均衡化。确定DRAM设备的响应时间包括使用总线将逻辑1写入DRAM设备的存储器位置。随后，通过总线发出读命令，其中读指令寻址到DRAM设备的新写存储位置。然后，存储器控制器测量读取命令的发出和从DRAM设备接收的逻辑电路之间的经过时间，并且该经过时间是DRAM设备的响应时间。在确定每个DRAM器件的响应时间并且使用最长的响应时间之后，为耦合到总线的每个DRAM器件计算延迟，使得每个DRAM器件的时钟周期中的响应时间被耦合总线等于最长响应时间。通过将值写入至每个DRAM器件的至少一个寄存器，在连接到总线的每个DRAM器件的至少一个寄存器中编程延迟。

43. 发明授权

US6075744A Dram core refresh with reduced spike current 有权
标题翻译：惊人的核心刷新，减少尖峰电流
公开(公告)号：US6075744A
公开(公告)日：2000-06-13
申请号：US169376
申请日：1998-10-09
申请人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel
发明人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel
IPC分类号： G11C8/08 , G11C11/406 , G11C11/408 , G11C8/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C11/40615 , G11C11/4085 , G11C8/08 , G11C2211/4061 , G11C2211/4067
摘要： A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.
摘要翻译：一种用于将通过接口总线的通信开销减少到用于刷新操作的存储器设备的方法。这是通过刷新多个银行来响应单个命令来完成的。与普通存储器访问相比，通过改变在刷新操作期间的行感测和行预充电电流的电流分布，可实现多重量刷新。与普通内存访问不同，不需要数据，不需要快速访问时间。这允许使用不同的电路来传播电流来驱动电流以减少电流尖峰。扩展电流仍然保持在正常内存访问的时间内。

44. 发明授权

US08756395B2 Controlling DRAM at time DRAM ready to receive command when exiting power down 有权
标题翻译：在DRAM时刻控制DRAM，准备在断电时接收命令
公开(公告)号：US08756395B2
公开(公告)日：2014-06-17
申请号：US13406465
申请日：2012-02-27
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F13/00
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.
摘要翻译：在实施例中提供了存储器件和系统的操作方法。初始化操作在初始化序列期间以第一操作频率进行。然后在第二操作频率下执行存储器存取操作。第二个操作频率高于第一个操作频率。此外，存储器访问操作包括读取操作和写入操作。在实施例中，从串行存在检测装置读取表示第一操作频率和第二操作频率的信息。

45. 发明申请

US20080162759A1 METHOD AND APPARATUS FOR ADJUSTING THE PERFORMANCE OF A SYNCHRONOUS MEMORY SYSTEM 有权
标题翻译：调整同步存储器系统性能的方法和装置
公开(公告)号：US20080162759A1
公开(公告)日：2008-07-03
申请号：US12036598
申请日：2008-02-25
申请人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
发明人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
IPC分类号： G06F13/18
CPC分类号： G11C7/1048 , G06F13/1689 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.
摘要翻译：提供了一种用于调整存储器系统的性能的方法和装置。存储器系统包括主设备和从设备。存储器通道将主设备耦合到从设备，使得从设备经由存储器通道从主设备接收系统操作信息。从设备还包括用于在从设备内调谐电路的装置，从而提高存储器系统的性能。

46. 发明授权

US06842864B1 Method and apparatus for configuring access times of memory devices 失效
标题翻译：用于配置存储设备的访问时间的方法和装置
公开(公告)号：US06842864B1
公开(公告)日：2005-01-11
申请号：US09685014
申请日：2000-10-05
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G06F13/00
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.
摘要翻译：提供了用于初始化动态随机存取存储器（DRAM）装置的方法和装置，其中通过确定耦合到总线的多个DRAM装置中的每一个的响应时间来对信道进行均衡化。确定DRAM设备的响应时间包括使用总线将逻辑1写入DRAM设备的存储器位置。随后，通过总线发出读命令，其中读指令寻址到DRAM设备的新写存储位置。然后，存储器控制器测量读取命令的发出和从DRAM设备接收的逻辑电路之间的经过时间，并且该经过时间是DRAM设备的响应时间。在确定每个DRAM器件的响应时间并使用最长的响应时间之后，为耦合到总线的每个DRAM器件计算延迟，使得每个DRAM器件的时钟周期中的响应时间被耦合总线等于最长响应时间。通过将值写入至每个DRAM器件的至少一个寄存器，在连接到总线的每个DRAM器件的至少一个寄存器中编程延迟。

47. 发明授权

US06597616B2 DRAM core refresh with reduced spike current 失效
公开(公告)号：US06597616B2
公开(公告)日：2003-07-22
申请号：US10066042
申请日：2002-01-29
申请人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel
发明人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel
IPC分类号： G11C700
CPC分类号： G11C11/40618 , G11C8/08 , G11C11/406 , G11C11/40615 , G11C11/4085 , G11C2211/4061 , G11C2211/4067
摘要： A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.

48. 发明授权

US06553452B2 Synchronous memory device having a temperature register 有权
标题翻译：具有温度寄存器的同步存储器件
公开(公告)号：US06553452B2
公开(公告)日：2003-04-22
申请号：US10051957
申请日：2002-01-18
申请人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
发明人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
IPC分类号： G06F1200
CPC分类号： G11C7/1048 , G06F13/1689 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A synchronous dynamic random access memory device having an array of dynamic memory cells. The memory device includes input receiver circuitry to sample a value that is representative of a range of temperatures. In addition, the memory device includes a programmable register, coupled to the input receiver circuitry, to store the value that is representative of the range of temperatures.
摘要翻译：一种具有动态存储单元阵列的同步动态随机存取存储器件。存储器件包括用于对表示温度范围的值进行采样的输入接收器电路。此外，存储器件包括耦合到输入接收器电路的可编程寄存器，以存储代表温度范围的值。

49. 发明授权

US08920294B2 Suspension training device 有权
标题翻译：悬架培训装置
公开(公告)号：US08920294B2
公开(公告)日：2014-12-30
申请号：US12769612
申请日：2010-04-28
申请人： Paul G. Davis
发明人： Paul G. Davis
IPC分类号： A63B21/068 , A63B26/00 , A63B21/16
CPC分类号： A63B7/00 , A63B21/068 , A63B21/1663
摘要： A suspension training device, system and method for using the same is disclosed. A suspension training device includes an elongated strap, a handle at a first end of the elongated strap, a harness at a second end of the elongated strap, and one or more stops, each stop being affixed at a position along a length of the elongated strap between the handle and the harness. A gravity training system includes two or more suspension training devices. The suspension training devices can be suspending with a stationary object by the stops, such as the elongated strap being threaded between a door and a doorframe, to a desired length to allow a user to accomplish any number of exercises or gravity-resistant movement.
摘要翻译：公开了一种悬架训练装置及其使用方法。悬挂训练装置包括细长带，在细长带的第一端处的手柄，在细长带的第二端处的线束，以及一个或多个止挡件，每个止动件固定在沿着细长带的长度的位置手柄和线束之间的带子。重力训练系统包括两个或更多个悬架训练装置。悬架训练装置可以通过诸如细长带在门和门框之间螺纹连接的止动件与静止物体悬挂到期望的长度，以允许使用者完成任何数量的锻炼或抗重力运动。

50. 发明授权

US08504790B2 Memory component having write operation with multiple time periods 有权
标题翻译：存储器组件具有多个时间段的写入操作
公开(公告)号：US08504790B2
公开(公告)日：2013-08-06
申请号：US13424273
申请日：2012-03-19
申请人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
发明人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G06F13/1626 , G11C7/22 , G11C11/4076 , G11C2207/2218 , G11C2207/229
摘要： A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.
摘要翻译：存储器控制器芯片执行用于将数据存储在包括具有动态随机存取存储单元的存储器核心的存储器芯片中的方法。该方法包括向存储器芯片的第一接口发送写命令，其中写命令指定写操作。在发送写命令之后，存储器控制器芯片等待与由存储芯片存储写入命令的时间段对应的第一时间段，并且将与写入操作相关联的数据发送到存储器芯片的第二接口，其中所述数据的发送在第二时间段之后发生，在所述第一时间段之后的所述第二时间段，使得发送所述写入命令并发送所述数据被隔开第一预定延迟时间，所述第一预定延迟时间包括所述第一时间段和第二个时期。

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