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41. 发明申请

US20120241839A1 SPLIT-GATE NON-VOLATILE MEMORY CELLS HAVING IMPROVED OVERLAP TOLERANCE 有权
标题翻译：具有改进的覆盖容忍度的分离栅非易失性记忆细胞
公开(公告)号：US20120241839A1
公开(公告)日：2012-09-27
申请号：US13448531
申请日：2012-04-17
申请人： TED R. WHITE , Gowrishankar L. Chindalore , Brian A. Winstead
发明人： TED R. WHITE , Gowrishankar L. Chindalore , Brian A. Winstead
IPC分类号： H01L27/088
CPC分类号： H01L29/42332 , H01L21/28273 , H01L27/11524 , H01L29/42328 , H01L29/7881
摘要： Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.
摘要翻译：实施例包括形成为具有控制栅极和选择栅极的分离栅极非易失性存储器单元，其中控制栅极的至少一部分形成在选择栅极上。在选择栅极和控制栅极之间形成电荷存储层。选择栅极使用第一导电层和第二导电层形成。第二导电层形成在第一导电层之上，并且具有比第一导电层更低的电阻率。在一个实施例中，第一导电层是多晶硅，第二导电层是氮化钛（TiN）。在另一个实施例中，第二导电层可以是硅化物或其它导电材料，或者具有比第一导电层低的电阻率的导电材料的组合。

42. 发明授权

US08163615B1 Split-gate non-volatile memory cell having improved overlap tolerance and method therefor 有权
标题翻译：分离门非易失性存储单元具有改进的重叠公差及其方法
公开(公告)号：US08163615B1
公开(公告)日：2012-04-24
申请号：US13052529
申请日：2011-03-21
申请人： Ted R. White , Gowrishankar L. Chindalore , Brian A. Winstead
发明人： Ted R. White , Gowrishankar L. Chindalore , Brian A. Winstead
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L27/11524 , H01L29/42328 , H01L29/7881
摘要： A method for forming a split-gate non-volatile memory (NVM) cell includes forming a first gate layer over a semiconductor substrate; forming a conductive layer over the first gate layer; patterning the first gate layer and the conductive layer to form a first sidewall, wherein the first sidewall comprises a sidewall of the first gate layer and a sidewall of the conductive layer; forming a first dielectric layer over the conductive layer and the semiconductor substrate, wherein the first dielectric layer overlaps the first sidewall; forming a second gate layer over the first dielectric layer, wherein the second gate layer is formed over the conductive layer and the first gate layer and overlaps the first sidewall; and patterning the first gate layer and the second gate layer to form a first gate and a second gate, respectively, of the split-gate NVM cell, wherein the second gate overlaps the first gate and a portion of the conductive layer remains between the first gate and the second gate.
摘要翻译：一种分离栅极非易失性存储器（NVM）单元的形成方法包括在半导体衬底上形成第一栅极层; 在所述第一栅极层上形成导电层; 图案化第一栅极层和导电层以形成第一侧壁，其中第一侧壁包括第一栅极层的侧壁和导电层的侧壁; 在所述导电层和所述半导体衬底之上形成第一电介质层，其中所述第一电介质层与所述第一侧壁重叠; 在所述第一介电层上形成第二栅极层，其中所述第二栅极层形成在所述导电层和所述第一栅极层上并与所述第一侧壁重叠; 以及图案化所述第一栅极层和所述第二栅极层，以分别形成所述分裂栅极NVM单元的第一栅极和第二栅极，其中所述第二栅极与所述第一栅极重叠，并且所述导电层的一部分保留在所述第一栅极门和第二门。

43. 发明授权

US07764550B2 Method of programming a non-volatile memory 有权
标题翻译：非易失性存储器的编程方法
公开(公告)号：US07764550B2
公开(公告)日：2010-07-27
申请号：US12277404
申请日：2008-11-25
申请人： Mohammed Suhail , Frank K. Baker, Jr. , Gowrishankar L. Chindalore
发明人： Mohammed Suhail , Frank K. Baker, Jr. , Gowrishankar L. Chindalore
IPC分类号： G11C16/04
CPC分类号： G11C16/3454 , G11C16/10 , G11C16/349
摘要： A memory system including non-volatile memory cells. The memory system includes program circuitry that programs cells to a first threshold voltage or a second threshold voltage based on the number of times that cells of the memory system have been erased. In one embodiment, the threshold voltage is reduced when any set of cells of the memory system have been erased a specific number of times.
摘要翻译：包括非易失性存储单元的存储器系统。存储器系统包括基于存储器系统的单元已经被擦除的次数将单元编程为第一阈值电压或第二阈值电压的程序电路。在一个实施例中，当存储器系统的任何一组单元已被擦除特定次数时，阈值电压被降低。

44. 发明申请

US20100078703A1 SPLIT-GATE NON-VOLATILE MEMORY CELL AND METHOD 有权
标题翻译：分离门非挥发性记忆细胞和方法
公开(公告)号：US20100078703A1
公开(公告)日：2010-04-01
申请号：US12241786
申请日：2008-09-30
申请人： Brian A. Winstead , Gowrishankar L. Chindalore , Konstantin V. Loiko , Horacio P. Gasquet
发明人： Brian A. Winstead , Gowrishankar L. Chindalore , Konstantin V. Loiko , Horacio P. Gasquet
IPC分类号： H01L29/792 , H01L21/8246 , H01L21/336
CPC分类号： H01L29/66833 , H01L29/42328 , H01L29/42344 , H01L29/66537 , H01L29/66636 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate.
摘要翻译：公开了一种在半导体衬底上制造非易失性存储单元的方法。选择栅极结构形成在衬底上。控制栅结构具有侧壁。在与侧壁相邻的区域中的衬底上形成外延层。在外延层上形成电荷存储层。在电荷存储层上形成控制栅极。这允许在选择栅极下的原位掺杂外延层而不需要反掺杂。避免反掺杂是有益的，因为反掺杂降低了电荷迁移率并增加了控制阈值电压的难度。此外，可以在衬底中形成凹部，并且在凹部中形成外延层，并且可以在形成外延层之前通过凹槽进入在选择栅极下方的区域中的衬底中的晕圈注入。

45. 发明授权

US07649781B2 Bit cell reference device and methods thereof 有权
标题翻译：比特单元参考装置及其方法
公开(公告)号：US07649781B2
公开(公告)日：2010-01-19
申请号：US11435944
申请日：2006-05-17
申请人： Ronald J. Syzdek , Gowrishankar L. Chindalore
发明人： Ronald J. Syzdek , Gowrishankar L. Chindalore
IPC分类号： G11C16/06
CPC分类号： G11C7/062 , G11C7/14 , G11C16/28 , G11C16/3427 , G11C2207/063
摘要： A memory device is disclosed. A reference device of the memory includes a trimmable current source and a fixed current source. Currents provided by each source are summed to provide a reference current to a sense amplifier. The sense amplifier senses the state of a bit cell by comparing a current from the bit cell, representative of a logic value, to the reference current. By basing the reference current on both a fixed and a trimmable current source, the reference device can be trimmed to compensate for process and operating characteristics of the device, while maintaining a minimum reference current in the event of a disturb mechanism that results in loss of the current provided by the trimmable current source.
摘要翻译：公开了一种存储器件。存储器的参考装置包括可调整电流源和固定电流源。每个源提供的电流被相加以向读出放大器提供参考电流。感测放大器通过将来自代表逻辑值的位单元的电流与参考电流进行比较来感测比特单元的状态。通过将参考电流设置在固定电流源和可调整电流源上，可以对参考装置进行修整，以补偿器件的工艺和工作特性，同时在造成损失的干扰机制的情况下保持最小参考电流由可调电流源提供的电流。

46. 发明授权

US07544980B2 Split gate memory cell in a FinFET 有权
标题翻译： FinFET中的分离栅极存储单元
公开(公告)号：US07544980B2
公开(公告)日：2009-06-09
申请号：US11342155
申请日：2006-01-27
申请人： Gowrishankar L. Chindalore , Craig T. Swift
发明人： Gowrishankar L. Chindalore , Craig T. Swift
IPC分类号： H01L29/06
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/0466 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/785 , H01L29/792
摘要： A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.
摘要翻译：使用半导体鳍片实现存储器单元，其中沟道区域沿着源极和漏极区域之间的鳍片的侧壁。通道区域的一部分具有与其相邻的选择栅极，而另一部分具有与其相邻的控制栅极，其间具有电荷存储结构。在一些实施例中，独立的控制栅极结构位于鳍的相对侧壁附近，以便实现两个存储单元。

47. 发明授权

US07491600B2 Nanocrystal bitcell process integration for high density application 有权
标题翻译：纳米晶体位元工艺集成，适用于高密度应用
公开(公告)号：US07491600B2
公开(公告)日：2009-02-17
申请号：US11267442
申请日：2005-11-04
申请人： Erwin J. Prinz , Gowrishankar L. Chindalore , Paul A. Ingersoll
发明人： Erwin J. Prinz , Gowrishankar L. Chindalore , Paul A. Ingersoll
IPC分类号： H01L21/8234 , H01L21/8244
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42332
摘要： A method for making a multibit non-volatile memory cell structure is provided herein. In accordance with the method, a semiconductor substrate (101) is provided, and first and second sets of memory stacks (103, 105, 107, and 109) are formed on the substrate, each memory stack including a control gate (111) and a layer of memory material (113). A source/drain region (123) is then formed between the first and second sets of memory stacks, and a silicide layer (125) is formed over the source/drain region.
摘要翻译：本文提供了一种制造多位非易失性存储单元结构的方法。根据该方法，提供半导体衬底（101），并且在衬底上形成第一和第二组存储堆叠（103,105,107和109），每个存储堆包括控制栅极（111）和一层记忆材料（113）。然后在第一组和第二组存储器堆之间形成源极/漏极区（123），并且在源极/漏极区域上形成硅化物层（125）。

48. 发明授权

US07195983B2 Programming, erasing, and reading structure for an NVM cell 有权
标题翻译： NVM单元的编程，擦除和读取结构
公开(公告)号：US07195983B2
公开(公告)日：2007-03-27
申请号：US10930892
申请日：2004-08-31
申请人： Gowrishankar L. Chindalore , James David Burnett , Craig T. Swift , Ramachandran Muralidhar
发明人： Gowrishankar L. Chindalore , James David Burnett , Craig T. Swift , Ramachandran Muralidhar
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L29/1608 , H01L29/267 , H01L29/66833 , H01L29/7881
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.
摘要翻译：非易失性存储器（NVM）具有硅锗（SiGe）漏极和硅碳（SiC）源。作为SiC的源提供通道上的应力，其改善N沟道迁移率。 SiC也具有比衬底更大的带隙，这是硅。这导致通过冲击电离产生电子/空穴对更困难。因此，在读取期间使用SiC区域用于漏极是有利的。 SiGe用作编程和擦除的漏极。具有比硅衬底更小的带隙的SiGe通过在较低电压电平下通过产生电子/空穴对的冲击电离和通过频带隧穿产生电子空穴/对来改善擦除来改善编程。

49. 发明授权

US06898128B2 Programming of a memory with discrete charge storage elements 有权
标题翻译：用离散电荷存储元件对存储器进行编程
公开(公告)号：US06898128B2
公开(公告)日：2005-05-24
申请号：US10622353
申请日：2003-07-18
申请人： Erwin J. Prinz , Gowrishankar L. Chindalore
发明人： Erwin J. Prinz , Gowrishankar L. Chindalore
IPC分类号： G11C11/34 , G11C16/00 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/28
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3454 , G11C2216/06 , H01L21/28273
摘要： A non volatile memory (100) includes an array (102) of transistors (30) having discrete charge storage elements (40). The transistors are programmed by using a two step programming method (60) where a first step (68) is hot carrier injection (HCl) programming with low gate voltages. A second step (78) is selectively utilized on some memory cells to modify the injected charge distribution to enhance the separation of charge distribution between each memory bit within the transistor memory cell. The second step of programming is implemented without adding significant additional time to the programming operation. In one example, the first step injects electrons and the second step injects holes. The resulting distribution of the two steps removes electron charge in the central region of the storage medium.
摘要翻译：非易失性存储器（100）包括具有离散电荷存储元件（40）的晶体管（30）的阵列（102）。通过使用两步编程方法（60）对晶体管进行编程，其中第一步骤（68）是具有低栅极电压的热载流子注入（HCl）编程。选择性地在一些存储器单元上利用第二步骤（78）来修改注入的电荷分布，以增强在晶体管存储单元内的每个存储器位之间的电荷分布的分离。实现编程的第二步是在不增加编程操作的额外时间的情况下实现。在一个示例中，第一步骤注入电子，第二步骤注入孔。所得到的两个步骤的分布在存储介质的中心区域中去除电子电荷。

50. 发明授权

US07838363B2 Method of forming a split gate non-volatile memory cell 有权
标题翻译：形成分裂门非易失性存储单元的方法
公开(公告)号：US07838363B2
公开(公告)日：2010-11-23
申请号：US11931376
申请日：2007-10-31
申请人： Robert F. Steimle , Gowrishankar L. Chindalore , Matthew T. Herrick
发明人： Robert F. Steimle , Gowrishankar L. Chindalore , Matthew T. Herrick
IPC分类号： H01L21/00
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/66833
摘要： A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.
摘要翻译：一种方法通过提供半导体衬底并形成覆盖选择栅极形成分离栅极存储单元。选择栅极具有预定的高度并且与半导体衬底电绝缘。随后形成电荷存储层，覆盖并邻近选择栅极。随后通过电荷存储层形成与选择栅极相邻并分离的控制栅极。电荷存储层也位于控制栅极和半导体衬底之间。控制门最初具有高于选择门的预定高度的高度。控制栅极凹入到小于选择栅极的预定高度的控制栅极高度。源极和漏极形成在半导体衬底中。

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