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41. 发明公开

EP1590731A2 MODULARE EXPONENTIATION MIT RANDOMISIERTEN EXPONENTEN 审中-公开
标题翻译：在RANDOMIZED指数的模幂
公开(公告)号：EP1590731A2
公开(公告)日：2005-11-02
申请号：EP04704224.7
申请日：2004-01-22
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland
IPC分类号： G06F7/72
CPC分类号： H04L9/30 , G06F7/723 , G06F2207/7257 , H04L9/003 , H04L2209/08
摘要： In order to determine a result of a modular exponentiation, a randomization auxiliary number based on the product of the public key and of the private key is set to less than '1' in order to randomize the exponent. This randomization auxiliary number can be derived without special functionalities from the private RSA data record. This enables an low-effort exponent randomization to be universally carried out for each security protocol in order to carry out a digital signature that is secure from side channel attacks.

42. 发明公开

EP1543408A1 VORRICHTUNG UND VERFAHREN ZUM BERECHNEN EINER MULTIPLIKATION MIT EINER VERSCHIEBUNG DES MULTIPLIKANDEN 有权
标题翻译：装置和方法用于计算乘以被乘数的转变
公开(公告)号：EP1543408A1
公开(公告)日：2005-06-22
申请号：EP03782247.5
申请日：2003-11-28
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland , SEIFERT, Jean-PierreINTEL Corporation , SEDLAK, Holger
IPC分类号： G06F7/72
CPC分类号： G06F7/722 , G06F7/5332
摘要： A device for calculating a modular multiplication comprises a unit for analyzing (100) positions of the multiplier by using a look-ahead algorithm in order to obtain a multiplication shifting value (sm). In addition, a unit for determining (104) an intermediate result shifting value is provided that determines a positive intermediate result shifting value. A unit (106) then calculates a multiplicand shifting value (sc) as a difference between the intermediate result shifting value (sz) and the multiplication shifting value (sm). The intermediate result from the previous iteration step and from the multiplicand are then shifted (108) by the corresponding shifting quantities (sc and sz) in order to then carry out a three-operand addition (112) with the shifted values optionally while taking look-ahead parameters (vn and vc) into consideration. The shifting of the intermediate result and of the multiplicand with regard to a fixed module enables the more efficient use of shifters since the multiplication shifting value (sm), which has a tendency to be large, does not dictate the shifter dimensioning.

43. 发明公开

EP1499954A2 BERECHNUNG EINES ERGEBNISSES EINER MODULAREN MULTIPLIKATION 有权
标题翻译：计算模乘的结果
公开(公告)号：EP1499954A2
公开(公告)日：2005-01-26
申请号：EP03727389.3
申请日：2003-04-28
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland , SEDLAK, Holger , SEIFERT, Jean-Pierre
IPC分类号： G06F7/72
CPC分类号： G06F7/722
摘要： The aim of the invention is to calculate a result of a modular multiplication of a first operand (A) and of a second operand (B) with regard to a modulus (N), said operands having a length of 2 n bits. To this end, the operands and the modulus are reduced into suboperands of half the length and are fed to a control device (14). Said control device controls an MMD device for performing a MultModDiv operation according to a predetermined step sequence with corresponding input operands (12a, 12b) and MMD moduli (12c) in order to obtain integral quotient values (Q(i)) and residual values (R(i)) with regard to the MMD modulus at an output (12d). A combining device (16) serves to combine integral quotient values and residual values from predetermined steps of the step sequence in order to obtain the result. Reducing a modular multiplication of operands e.g. the length of 2 n bits into a number of MMD operations with operands having a length of n bits, therefore half the length, enables cryptographic algorithms having long operands to be efficiently performed on an arithmetic-logic unit developed for shorter operands whereby increasing security demands in accordance with longer codes are efficiently fulfilled with the use of existing circuits.

44. 发明公开

EP1488428A2 REGISTERZELLE UND VERFAHREN ZUM SCHREIBEN AUF DIE REGISTERZELLE 有权
标题翻译：寄存器单元和方法写在寄存器单元
公开(公告)号：EP1488428A2
公开(公告)日：2004-12-22
申请号：EP03712035.9
申请日：2003-03-17
申请人： Infineon Technologies AG
发明人： ELBE, Astrid , FISCHER, Wieland , JANSSEN, Norbert , ROEMER, Tanja , SEDLAK, Holger , SEIFERT, Jean-Pierre
IPC分类号： G11C11/41
CPC分类号： G11C7/22 , G11C2207/007 , G11C2207/2227
摘要： The invention relates to a register cell which comprises a first input (10) for a data unit to be written into said register cell. The register cell further comprises a second input (12) for a negated data unit to be written into the register cell. A first pair (14) of cross-coupled inverters (14a, 14b) can be coupled with the first input (10) as the first memory circuit. A second pair of cross-coupled inverters (16a, 16b) can be coupled with the second input (12) as the second memory circuit. The use of two cross-coupled pairs of inverters allows to initialize (30) the first input (10) and the second input (12) of the register either at a high voltage status (precharge) or at a low voltage status (discharge) in such a manner as to render the power consumption of the register cell from one cycle to the next more uniform.

45. 发明公开

EP1468518A1 VORRICHTUNG UND VERFAHREN ZUM ERZEUGEN EINES BEFEHLSCODES FÜR EIN KRYPTOGRAMM 有权
标题翻译：设备和方法产生命令编码一种密码
公开(公告)号：EP1468518A1
公开(公告)日：2004-10-20
申请号：EP03731710.4
申请日：2003-01-23
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland , SEIFERT, Jean-Pierre
IPC分类号： H04L9/06
CPC分类号： H04L9/003 , H04L2209/12
摘要： Disclosed is a device for generating a command code with a plurality of command code words, comprising a device (10) making available a command group with commands from a set of commands. The commands from the command group can be executed alternatively to each other depending on a decision in a program. The inventive device also comprises a device (12) assigning command code words to the commands of the command group. Said code words are different from each other and are configured in such a way that a feature of a circuit which depends on the processing of the command code words lies in a predefined range for the command code words of the command group, whereby decisions in the program which depend on secret data can no longer be intercepted by means of side channel attacks detecting the feature, such as the circuit drawing power. As a consequence, a cryptoprocessor operates in a more efficient and secure manner without any additional circuit complexity.

46. 发明公开

EP1454260A2 VERFAHREN UND VORRICHTUNG ZUM ABSICHERN EINER EXPONENTIATIONS-BERECHNUNG MITTELS DEM CHINESISCHEN RESTSATZ (CRT) 有权
标题翻译：方法和装置用于固定幂计算使用Chinese REST SET（CRT）
公开(公告)号：EP1454260A2
公开(公告)日：2004-09-08
申请号：EP02785220.1
申请日：2002-10-15
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland , SEIFERT, Jean-Pierre
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F7/723 , G06F2207/7271
摘要： The invention relates to a method for securing an exponentiation calculation by means of the Chinese remainder theorem, wherein the joining step (16) in particular, during which, preferably, the joining algorithm according to Garner is used, is monitored (18) for correctness prior to the output (24) of the result of the joining step. Verification occurs directly before the output of the result of the exponentiation calculation of the joining algorithm in order to be able to prevent outputs of an incorrect result, for example as a result of a hardware error attack, so that said error attack can be warded off.

47. 发明授权

EP1499954B1 BERECHNUNG EINES ERGEBNISSES EINER MODULAREN MULTIPLIKATION 有权
标题翻译：计算模乘的结果
公开(公告)号：EP1499954B1
公开(公告)日：2007-01-17
申请号：EP03727389.3
申请日：2003-04-28
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland , SEDLAK, Holger , SEIFERT, Jean-Pierre
IPC分类号： G06F7/72
CPC分类号： G06F7/722
摘要： The aim of the invention is to calculate a result of a modular multiplication of a first operand (A) and of a second operand (B) with regard to a modulus (N), said operands having a length of 2 n bits. To this end, the operands and the modulus are reduced into suboperands of half the length and are fed to a control device (14). Said control device controls an MMD device for performing a MultModDiv operation according to a predetermined step sequence with corresponding input operands (12a, 12b) and MMD moduli (12c) in order to obtain integral quotient values (Q ) and residual values (R ) with regard to the MMD modulus at an output (12d). A combining device (16) serves to combine integral quotient values and residual values from predetermined steps of the step sequence in order to obtain the result. Reducing a modular multiplication of operands e.g. the length of 2 n bits into a number of MMD operations with operands having a length of n bits, therefore half the length, enables cryptographic algorithms having long operands to be efficiently performed on an arithmetic-logic unit developed for shorter operands whereby increasing security demands in accordance with longer codes are efficiently fulfilled with the use of existing circuits.

48. 发明授权

EP1488428B1 REGISTERZELLE UND VERFAHREN ZUM SCHREIBEN AUF DIE REGISTERZELLE 有权
标题翻译：寄存器单元和方法写在寄存器单元
公开(公告)号：EP1488428B1
公开(公告)日：2006-09-06
申请号：EP03712035.9
申请日：2003-03-17
申请人： Infineon Technologies AG
发明人： ELBE, Astrid , FISCHER, Wieland , JANSSEN, Norbert , ROEMER, Tanja , SEDLAK, Holger , SEIFERT, Jean-Pierre
IPC分类号： G11C11/41
CPC分类号： G11C7/22 , G11C2207/007 , G11C2207/2227
摘要： The invention relates to a register cell which comprises a first input (10) for a data unit to be written into said register cell. The register cell further comprises a second input (12) for a negated data unit to be written into the register cell. A first pair (14) of cross-coupled inverters (14a, 14b) can be coupled with the first input (10) as the first memory circuit. A second pair of cross-coupled inverters (16a, 16b) can be coupled with the second input (12) as the second memory circuit. The use of two cross-coupled pairs of inverters allows to initialize (30) the first input (10) and the second input (12) of the register either at a high voltage status (precharge) or at a low voltage status (discharge) in such a manner as to render the power consumption of the register cell from one cycle to the next more uniform.

49. 发明公开

EP1661069A2 PROZESSORSCHALTUNG UND VERFAHREN ZUM ZUORDNEN EINES LOGIKCHIPS ZU EINEM SPEICHERCHIP 有权
标题翻译：处理器电路和方法用于识别逻辑芯片，存储芯片
公开(公告)号：EP1661069A2
公开(公告)日：2006-05-31
申请号：EP04763500.8
申请日：2004-07-26
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland , SEIFERT, Jean-Pierre
IPC分类号： G06K19/07
CPC分类号： G07F7/1008 , G06F21/73 , G06F21/79 , G06Q20/341 , G06Q20/3576 , G06Q20/40975
摘要： A processor chip comprising a logic chip (12) with a logic circuit (12a) and a non-volatile memory (12b) in addition to a memory chip (14) with a non-volatile memory. A key (k) is stored in the non-volatile memory (12b) of the logic chip (12) using electric safeguards (13a,13b,13c). Personalization information (13d), signaling that the logic chip is allocated to a memory chip, is also stored. A chip identification (m), which is encrypted with the key (k), is stored in the memory chip (14) in an ID storage area (16). When the processor is run up, initial verification occurs as to whether the encrypted logic chip identification stored in the memory chip is authentic or not. the logic chip can thus be personalized in a simple and economical manner in order to protect against attacks with regard to remoteness or manipulation of the memory chip.

50. 发明授权

EP1543408B1 VORRICHTUNG UND VERFAHREN ZUM BERECHNEN EINER MULTIPLIKATION MIT EINER VERSCHIEBUNG DES MULTIPLIKANDEN 有权
标题翻译：装置和方法用于计算乘以被乘数的转变
公开(公告)号：EP1543408B1
公开(公告)日：2006-01-18
申请号：EP03782247.5
申请日：2003-11-28
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland , SEIFERT, Jean-Pierre INTEL Corporation , SEDLAK, Holger
IPC分类号： G06F7/72
CPC分类号： G06F7/722 , G06F7/5332
摘要： A device for calculating a modular multiplication comprises a unit for analyzing (100) positions of the multiplier by using a look-ahead algorithm in order to obtain a multiplication shifting value (sm). In addition, a unit for determining (104) an intermediate result shifting value is provided that determines a positive intermediate result shifting value. A unit (106) then calculates a multiplicand shifting value (sc) as a difference between the intermediate result shifting value (sz) and the multiplication shifting value (sm). The intermediate result from the previous iteration step and from the multiplicand are then shifted (108) by the corresponding shifting quantities (sc and sz) in order to then carry out a three-operand addition (112) with the shifted values optionally while taking look-ahead parameters (vn and vc) into consideration. The shifting of the intermediate result and of the multiplicand with regard to a fixed module enables the more efficient use of shifters since the multiplication shifting value (sm), which has a tendency to be large, does not dictate the shifter dimensioning.

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