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41. 发明授权

US08766719B2 Digitally-controlled power amplifier with bandpass filtering/transient waveform control and related digitally-controlled power amplifier cell 有权
标题翻译：具有带通滤波/瞬态波形控制和相关数字控制功率放大器单元的数字控制功率放大器
公开(公告)号：US08766719B2
公开(公告)日：2014-07-01
申请号：US13484268
申请日：2012-05-30
申请人： Jie-Wei Lai , Meng-Hsiung Hung , Robert Bogdan Staszewski
发明人： Jie-Wei Lai , Meng-Hsiung Hung , Robert Bogdan Staszewski
IPC分类号： H03F1/00
CPC分类号： H03F3/68 , H03F3/193 , H03F3/211 , H03F3/2171 , H03F3/2176 , H03F3/2178
摘要： A digitally-controlled power amplifier (DPA) with bandpass filtering includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.
摘要翻译：具有带通滤波的数字控制功率放大器（DPA）包括射频（RF）时钟输入，幅度控制字（ACW）输入和多个DPA信元。 RF时钟输入被布置用于接收RF时钟。 ACW输入被安排用于接收数字ACW信号。 DPA单元耦合到RF时钟和数字ACW信号，其中响应于数字ACW信号的至少一位，DPA单元中的至少一个逐渐导通和截止。

42. 发明授权

US08669890B2 Method and apparatus of estimating/calibrating TDC mismatch 有权
标题翻译：估计/校准TDC失配的方法和装置
公开(公告)号：US08669890B2
公开(公告)日：2014-03-11
申请号：US13610827
申请日：2012-09-11
申请人： Chi-Hsueh Wang , Robert Bogdan Staszewski , Yi-Hsien Cho
发明人： Chi-Hsueh Wang , Robert Bogdan Staszewski , Yi-Hsien Cho
IPC分类号： H03M1/06
CPC分类号： G04F10/005
摘要： A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.
摘要翻译：一种估计时间 - 数字转换器（TDC）的不匹配的方法包括：捕获相位误差样本; 计算相位误差样本与相位误差样本的期望值之间的差异; 以及基于所述计算步骤调整所述TDC的校正增益。估计TDC不匹配的另一种方法包括：捕获TDC输出码样本; 分别存储对应于不同TDC值的多个累加值，其中每个累积值记录TDC输出代码样本携带TDC值的次数; 基于累积值计算期望值; 计算积累值和期望值之间的差异; 以及基于所述计算步骤调整所述TDC的校正增益。

43. 发明授权

US08660209B2 Transmitter and frequency deviation reduction method thereof 有权
标题翻译：发射机及其频偏减少方法
公开(公告)号：US08660209B2
公开(公告)日：2014-02-25
申请号：US13614312
申请日：2012-09-13
申请人： Kai-Peng Kao , Chi-Hsueh Wang , Robert Bogdan Staszewski , Ping-Ying Wang
发明人： Kai-Peng Kao , Chi-Hsueh Wang , Robert Bogdan Staszewski , Ping-Ying Wang
IPC分类号： H03C1/52 , H04L27/04
CPC分类号： H04L27/12 , H04L27/361
摘要： A transmitter is provided. The transmitter includes a phase/frequency deviation input, a controller and a frequency modulating path. The phase/frequency deviation input receives multiple phase/frequency deviation samples. The controller outputs a modified phase/frequency deviation signal and generates a phase/frequency deviation carry-out signal in response to the phase/frequency deviation samples and a previous time sample of the phase/frequency deviation carry-out signal. The frequency modulating path performs frequency modulation in response to the modified phase/frequency deviation signal and outputs a frequency modulated carrier signal.
摘要翻译：提供发射机。发射机包括相位/频率偏差输入，控制器和频率调制路径。相位/频率偏差输入接收多个相位/频率偏差样本。控制器输出修正的相位/频率偏差信号，并响应于相位/频率偏差采样和相位/频率偏移进行输出信号的先前时间采样而产生相位/频率偏移进行输出信号。频率调制路径响应于修改的相位/频率偏差信号执行频率调制，并输出调频载波信号。

44. 发明申请

US20120027143A1 CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF 有权
标题翻译：用于产生具有输入时钟的非谐波关系的输出时钟的时钟发生器及其相关时钟生成方法
公开(公告)号：US20120027143A1
公开(公告)日：2012-02-02
申请号：US13170197
申请日：2011-06-28
申请人： Chi-Hsueh Wang , Robert Bogdan Staszewski
发明人： Chi-Hsueh Wang , Robert Bogdan Staszewski
IPC分类号： H04L7/00
CPC分类号： H03K5/131 , H03L7/0996
摘要： One clock generator includes an oscillator block, a delay circuit, and an output block. The oscillator block provides a first clock of multiple phases. The delay circuit delays at least one of said multiple phases of said first clock to generate a second clock of multiple phases. The output block generates a third clock by selecting signals from said multiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. Another exemplary clock generator includes an oscillator block and an output block. The oscillator block includes an oscillator arranged to provide a first clock, and a delay locked loop arranged to generate a second clock according to said first clock. The output block generates a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock.
摘要翻译：一个时钟发生器包括一个振荡器模块，一个延迟电路和一个输出模块。振荡器模块提供多个阶段的第一个时钟。所述延迟电路延迟所述第一时钟的所述多个相位中的至少一个以产生多相的第二时钟。输出块通过从所述第二时钟的所述多个相位选择信号来产生第三时钟，其中所述第三时钟与所述第一时钟具有非谐波关系。另一示例性时钟发生器包括振荡器模块和输出模块。振荡器模块包括布置成提供第一时钟的振荡器和布置成根据所述第一时钟产生第二时钟的延迟锁定环。输出块通过从所述多个相位选择信号来产生第三时钟，其中所述第三时钟与所述第一时钟具有非谐波关系。

45. 发明申请

US20110148676A1 DIGITAL PHASE LOCKED LOOP WITH DITHERING 审中-公开
标题翻译：数字相位锁定环
公开(公告)号：US20110148676A1
公开(公告)日：2011-06-23
申请号：US13038885
申请日：2011-03-02
申请人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
发明人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
IPC分类号： H03M1/20
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。抖动电路耦合到参考信号，并将短序列抖动信号注入到参考信号中，以便克服量化噪声，从而改进整数信道的RMS相位误差检测。

46. 发明申请

US20100271131A1 INTEGRATED POWER AMPLIFIER 有权
公开(公告)号：US20100271131A1
公开(公告)日：2010-10-28
申请号：US12830898
申请日：2010-07-06
申请人： Robert Bogdan Staszewski , See Taur Lee
发明人： Robert Bogdan Staszewski , See Taur Lee
IPC分类号： H03F3/45 , H03F3/16
CPC分类号： H03F3/189 , H03F3/211 , H03F3/602 , H03F2200/541
摘要： Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.

47. 发明申请

US20090207940A1 Predistortion Calibration In A Transceiver Assembly 审中-公开
标题翻译：收发器组件中的预失真校准
公开(公告)号：US20090207940A1
公开(公告)日：2009-08-20
申请号：US12432447
申请日：2009-04-29
申请人： Robert Bogdan Staszewski , Dirk Leipold
发明人： Robert Bogdan Staszewski , Dirk Leipold
IPC分类号： H04L25/03 , H04L25/49
CPC分类号： H03F1/3282 , H03F1/0211 , H03F1/3247 , H03F2200/331
摘要： Systems and methods are provided for calibrating a digital predistorter in an integrated transceiver circuit. A digital transmitter path provides a signal from a digital input. The transmitter path includes a digital predistorter that predistorts the digital input to mitigate nonlinearities associated with a power amplifier. The integrated transceiver circuit further includes a receiver path associated with the digital transmitter path. A coupling element provides the signal from the transmitter path to the receiver path. A signal evaluator determines values for at least one parameter associated with the digital predistorter based on the signal.
摘要翻译：提供了用于校准集成收发器电路中的数字预失真器的系统和方法。数字发射器路径提供来自数字输入的信号。发射机路径包括数字预失真器，其预失真数字输入以减轻与功率放大器相关联的非线性。集成收发器电路还包括与数字发送器路径相关联的接收器路径。耦合元件提供从发射机路径到接收机路径的信号。信号评估器基于该信号确定与数字预失真器相关联的至少一个参数的值。

48. 发明申请

US20090096525A1 Power amplifier 有权
标题翻译：功率放大器
公开(公告)号：US20090096525A1
公开(公告)日：2009-04-16
申请号：US12134464
申请日：2008-06-06
申请人： Robert Bogdan Staszewski , See Taur Lee , Dirk Leipold
发明人： Robert Bogdan Staszewski , See Taur Lee , Dirk Leipold
IPC分类号： H03F3/21 , H03F3/68 , H03F1/02
CPC分类号： H03F3/189 , H03F3/211 , H03F3/602 , H03F2200/541
摘要： Methods to implement power control in a digital power amplifier are described.
摘要翻译：描述了在数字功率放大器中实现功率控制的方法。

49. 发明申请

US20080317189A1 BINARY RIPPLE COUNTER SAMPLING WITH ADJUSTABLE DELAYS 有权
标题翻译：二进制RIPPLE计数器采用可调延迟
公开(公告)号：US20080317189A1
公开(公告)日：2008-12-25
申请号：US12143008
申请日：2008-06-20
申请人： Jingchen Zhuang , Robert Bogdan Staszewski
发明人： Jingchen Zhuang , Robert Bogdan Staszewski
IPC分类号： G06M3/00 , H03D3/24
CPC分类号： H03K23/58 , H03K23/662
摘要： The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with adjustable delay elements that permit accurate sampling regardless of: delay mismatch between the sampler and a data path of the counter; the length of the counter; operating speed; or PVT variations.
摘要翻译：二进制纹波计数器的输出位用于控制这些输出位的采样，从而确保精确的采样。采样器具有可调延迟元件，允许精确采样，而不管采样器和计数器的数据通路之间的延迟不匹配：柜台的长度; 运行速度; 或PVT变化。

50. 发明申请

US20080157839A1 TIME-TO-DIGITAL CONVERTER WITH NON-INVERTING BUFFERS, TRANSMISSION GATES AND NON-LINEARITY CORRECTOR, SOC INCLUDING SUCH CONVERTER AND METHOD OF PHASE DETECTION FOR USE IN SYNTHESIZING A CLOCK SIGNAL 有权
标题翻译：具有非反相缓冲器，传输门和非线性校正器的时间到数字转换器，包括这种转换器的SOC以及用于合成时钟信号的相位检测方法
公开(公告)号：US20080157839A1
公开(公告)日：2008-07-03
申请号：US11690506
申请日：2007-03-23
申请人： Robert Bogdan Staszewski , Dirk Leipold , Wei Chen
发明人： Robert Bogdan Staszewski , Dirk Leipold , Wei Chen
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , H03L2207/50
摘要： A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals. Each one of the delay elements includes: (1) a non-inverting buffer configured to delay the clock signal by about twice a delay of an inverter to provide a buffer-delayed clock signal and (2) a first transmission gate coupled to the non-inverting buffer and configured to delay the clock signal by about the delay of an inverter to provide a first gate-delayed clock signal.
摘要翻译：时间数字转换器（TDC），包括TDC的片上系统，用于合成时钟信号的相位检测方法和用于TDC的非线性校正器。在一个实施例中，TDC包括被配置为接收时钟信号并产生延迟的时钟信号的延迟元件链。每个延迟元件包括：（1）非反相缓冲器，被配置为将时钟信号延迟约两倍的逆变器的延迟以提供缓冲器延迟的时钟信号，以及（2）耦合到非反相缓冲器的第一传输门反相缓冲器并且被配置为将时钟信号延迟大约逆变器的延迟以提供第一门延迟的时钟信号。

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