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41. 发明授权

US06329002B1 Food for inhibiting infection and treating gastritis, gastric and duodenal ulcers 失效
标题翻译：用于抑制感染和治疗胃炎，胃和十二指肠溃疡的食物
公开(公告)号：US06329002B1
公开(公告)日：2001-12-11
申请号：US09498668
申请日：2000-02-07
申请人： Hyun Mi Kim , Cheol Seong Heo , Jung Lyoul Lee , Hyung Soo Kim
发明人： Hyun Mi Kim , Cheol Seong Heo , Jung Lyoul Lee , Hyung Soo Kim
IPC分类号： A01N6300
CPC分类号： A23C9/1307 , A23C9/1232 , A23C9/1234 , A23L29/065 , A23Y2220/17 , A23Y2300/55 , A61K35/744 , A61K35/745 , A61K35/747 , A61K39/40 , A61K2039/505 , C07K16/121 , C07K2317/11 , C07K2317/23 , A61K2300/00
摘要： Live strains of Lactococcus sp. HY 49, Lactobacillus casei HY 2782, and Bifidobacterium longum HY 8001 maintained in nutritious foods, such as yogurt, imbue them with prophylactic and/or therapeutic properties. Such foods are beneficial in the prevention and/or treatment of gastritis, duodenal and gastric ulcers caused by infection from Helicobacter pylori (also referred to as H. pylori). The properties of these bacteria are boosted by the addition of egg yolk containing antibodies specific to H. pylori antigen derived from “fractionated H. pylori”.
摘要翻译：乳酸菌活菌株 HY49，干酪乳杆菌HY 2782和保持在营养食品例如酸奶中的双歧杆菌HY 8001使其具有预防和/或治疗性质。这些食物有利于预防和/或治疗由幽门螺杆菌感染引起的胃炎，十二指肠和胃溃疡（也称为幽门螺杆菌）。这些细菌的性质通过加入含有来源于“分级幽门螺杆菌”的幽门螺杆菌抗原特异性的蛋黄的蛋黄来加强。

42. 发明申请

US20140360737A1 CLAMPING STRUCTURE FOR MOUNTING REDUCER 审中-公开
标题翻译：用于安装减速器的夹紧结构
公开(公告)号：US20140360737A1
公开(公告)日：2014-12-11
申请号：US14100107
申请日：2013-12-09
申请人： Hyung Soo Kim
发明人： Hyung Soo Kim
IPC分类号： A62C35/68
CPC分类号： F16L3/00 , F16B2/185 , F16L3/006 , F16L3/1075 , F16L3/24
摘要： Disclosed herein is a clamping structure for mounting a reducer. The clamping structure include a clamp body 431 that is formed at opposite sides thereof with a door connecting portion 431a and a latch member connecting portion 431b to form a rectangular shape with one open side, and a clamp door 434 that can be rotated about a hinge pin 433 formed at the door connecting portion 431a, wherein the clamp door 431 is formed at one side thereof with a fastening portion, to which a latch portion of a latch member 450 is latched to allow a lever handle 446 of a lever member 440 to be pushed, and wherein the lever member 440 is coupled at one end thereof to the latch member connecting portion 450 of the clamp body 431 by a hinge 444 and is rotatably coupled at a middle thereof to the latch member 450 by a hinge 454 of the latch member 450.
摘要翻译：这里公开了一种用于安装减速器的夹紧结构。夹紧结构包括：夹具主体431，其在其相对侧形成有门连接部分431a和闩锁构件连接部分431b，以形成具有一个开放侧面的矩形形状;以及夹具门434，其能够围绕铰链旋转销433形成在门连接部分431a处，其中夹具门431在其一侧形成有紧固部分，闩锁构件450的闩锁部分锁定到该紧固部分，以允许杆构件440的杠杆手柄446 并且其中杠杆构件440的一端通过铰链444联接到夹具主体431的闩锁构件连接部分450，并且通过铰链444的铰链454可旋转地联接到闩锁构件450的中间闩构件450。

43. 发明授权

US08373456B2 Domain crossing circuit of a semiconductor memory apparatus 有权
标题翻译：半导体存储装置的域交叉电路
公开(公告)号：US08373456B2
公开(公告)日：2013-02-12
申请号：US12486281
申请日：2009-06-17
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/00
CPC分类号： H04L7/0338 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , H04L7/0045
摘要： The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.
摘要翻译：用于提高定时裕度的半导体存储装置的域交叉电路包括：采样器，其通过响应于时钟和内部输入信号产生的采样内部信号，边缘信息信号定义为输出定时采样内部信号和输出级，其允许采样内部信号与时钟同步，以响应于作为最终输出信号输出的边缘信息信号。

44. 发明授权

US08099620B2 Domain crossing circuit of a semiconductor memory apparatus 失效
标题翻译：半导体存储装置的域交叉电路
公开(公告)号：US08099620B2
公开(公告)日：2012-01-17
申请号：US12346675
申请日：2008-12-30
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G06F1/00 , G06F1/04 , G06F12/00 , H03K19/00 , H03L7/00 , G11C8/00
CPC分类号： G11C7/1051 , G06F1/12 , G11C7/1072 , G11C7/222
摘要： A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.
摘要翻译：半导体存储器装置的域交叉电路，域交叉电路包括在基本上相同的时钟周期产生的第一和第二计数信号，并且相对于相同位组合数据参考内部时钟信号表示预定的时钟差，以及数据处理单元，被配置为响应于与外部时钟信号同步的输入数据，基于第二计数信号提供对应于输入数据的输出数据。

45. 发明授权

US07949081B2 Phase detecting circuit and clock generating apparatus including the same 有权
标题翻译：相位检测电路和包括该相位检测电路的时钟发生装置
公开(公告)号：US07949081B2
公开(公告)日：2011-05-24
申请号：US12026384
申请日：2008-02-05
申请人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H04L7/04 , H03L7/00
CPC分类号： H03L7/0814 , H03L7/089
摘要： A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.
摘要翻译：相位检测电路包括：输出上拉控制信号的第一节点，输出下拉控制信号的第二节点;响应于预充电信号初始化第一和第二节点的电压电平的初始化单元; 接收接收机数据的数据输入单元，比较接收机时钟的相位和输入到数据输入单元的接收机数据的相位以控制第一和第二节点的电压电平的相位比较单元，以及充电/放电单元，其对施加到第一和第二节点的电荷进行充电或放电。

46. 发明授权

US07852132B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07852132B2
公开(公告)日：2010-12-14
申请号：US12340912
申请日：2008-12-22
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/06
CPC分类号： H03K3/0322 , H03K5/1504 , H03K2005/00208 , H03L7/083 , H03L7/24
摘要： A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.
摘要翻译：半导体集成电路包括PLL（锁相环）电路，其被配置为响应于参考时钟信号的频率产生控制电压，并且产生具有对应于控制电平的频率的PLL时钟信号电压和被配置为响应于PLL时钟信号而振荡输出时钟信号的压控振荡器，并且允许PLL时钟信号具有对应于控制电压电平的频率。

47. 发明授权

US07721559B2 Multi-type air conditioner and method for controlling the same 有权
标题翻译：多型空调及其控制方法
公开(公告)号：US07721559B2
公开(公告)日：2010-05-25
申请号：US11274329
申请日：2005-11-16
申请人： Jae Heuk Choi , Yoon Been Lee , Baik Young Chung , Se Dong Chang , Hyung Soo Kim
发明人： Jae Heuk Choi , Yoon Been Lee , Baik Young Chung , Se Dong Chang , Hyung Soo Kim
IPC分类号： F25B7/00 , F25B1/00 , F25B1/10 , F04B23/04
CPC分类号： F25B31/002 , F25B13/00 , F25B2313/006 , F25B2313/0253 , F25B2400/075 , F25B2500/01 , F25B2600/02 , F25B2700/2105 , F25B2700/2115 , F25B2700/21155
摘要： Multi-type air conditioner including a plurality of compressors, a plurality of temperature sensors mounted in the plurality of compressors for sensing temperatures in the compressors respectively, and an equalizing pipe in communication with the plurality of compressors, for uniform distribution of oil among the plurality of compressors according to the temperatures sensed at the plurality of temperature sensors respectively, thereby distributing oil among the compressors uniformly at an exact time point at which the oil is distributed among the compressors non-uniformly, not only to permit improvement of the performance of the compressors, but also to permit improvement performance of the air conditioner having the compressors.
摘要翻译：包括多个压缩机的多型空调器，安装在多个压缩机中的多个温度传感器，分别用于感测压缩机中的温度，以及与多个压缩机连通的均衡管道，用于在多个压缩机之间均匀分配油的压缩机分别根据在多个温度传感器处感测到的温度，从而在压缩机中均匀地分配油的精确时间点均匀地分配压缩机之间的油，不仅可以改善压缩机的性能，压缩机，而且还允许具有压缩机的空调的改进性能。

48. 发明申请

US20100117702A1 DUTY CYCLE CORRECTION APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME 有权
标题翻译：带周期校正装置和具有相同功能的半导体集成电路
公开(公告)号：US20100117702A1
公开(公告)日：2010-05-13
申请号：US12407727
申请日：2009-03-19
申请人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
发明人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00052 , H03L7/0814
摘要： A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.
摘要翻译：占空比校正装置包括：固定延迟单元，被配置为将固定延迟时间设置为DLL时钟信号，并产生延迟上升时钟信号; 可变延迟单元，被配置为响应于控制信号延迟所述DLL时钟信号并产生延迟下降时钟信号; 占空比校正单元，被配置为产生与延迟上升时钟信号和延迟下降时钟信号的边沿定时一致的校正上升时钟信号和校正下降时钟信号; 以及延迟控制单元，被配置为检测所述校正上升时钟信号和所述校正下降时钟信号的占空比，并产生所述控制信号。

49. 发明申请

US20100090736A1 DELAY LOCKED LOOP CIRCUIT AND MEMORY DEVICE HAVING THE SAME 有权
标题翻译：延迟锁定环路电路和具有该环路的存储器件
公开(公告)号：US20100090736A1
公开(公告)日：2010-04-15
申请号：US12346614
申请日：2008-12-30
申请人： Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/08
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0995 , H03L7/0998
摘要： A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled.
摘要翻译：一个DLL电路包括一个多相时钟信号产生单元，被配置为通过延迟基准时钟信号来产生一个单位延迟时间来产生多个多相时钟信号，并产生一个使能信号，当多个多相时钟信号中的一个同步时以及频率上的参考时钟信号，以及多相时钟信号选择单元，被配置为响应于第一控制信号而延迟多个多相时钟信号中的一个预定时间，以比较延迟的多相时钟信号的相位具有参考时钟信号的相位，并且将多个多相时钟信号中的一个作为延迟的时钟信号输出，其中当使能信号被使能时，延迟的时钟信号的相位与参考时钟信号的相位同步。

50. 发明申请

US20100061167A1 DATA OUTPUT CIRCUIT 有权
标题翻译：数据输出电路
公开(公告)号：US20100061167A1
公开(公告)日：2010-03-11
申请号：US12340882
申请日：2008-12-22
申请人： Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C11/4093
摘要： A data output circuit includes a pre-driving block configured to receive input data, generate a plurality of pull-up signals and pull-down signals, and change enable times of the pull-up signals and the pull-down signals in response to a plurality of control signals, and a main driving block configured to generate output data in response to the pull-up signals and the pull-down signals.
摘要翻译：数据输出电路包括：预驱动块，被配置为接收输入数据，产生多个上拉信号和下拉信号，以及响应于一个上拉信号和下拉信号改变使能时间多个控制信号和主驱动块，被配置为响应于上拉信号和下拉信号而产生输出数据。

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