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41. 发明申请

US20120104508A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120104508A1
公开(公告)日：2012-05-03
申请号：US13256866
申请日：2011-02-25
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/66545 , H01L29/7845
摘要： There is provided a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions formed on both sides of the channel region and embedded in the semiconductor substrate. The gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer. For an nMOSFET, the conductive layer has a compressive stress to apply a tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress to apply a compressive stress to the channel region.
摘要翻译：提供半导体结构及其制造方法。根据本发明的半导体结构包括：半导体衬底; 形成在半导体衬底上的沟道区; 形成在沟道区上的栅叠层; 以及形成在沟道区两侧并嵌入在半导体衬底中的源/漏区。栅极堆叠包括：形成在沟道区上的栅极电介质层; 以及位于栅介质层上的导电层。对于nMOSFET，导电层具有将压应力施加到沟道区的压应力; 并且对于pMOSFET，导电层具有拉伸应力以向沟道区域施加压应力。

42. 发明申请

US20110260214A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110260214A1
公开(公告)日：2011-10-27
申请号：US13063977
申请日：2011-02-24
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/0653 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7849
摘要： The present invention discloses a semiconductor device and a method for manufacturing the same, and relates to the field of semiconductor manufacturing. According to the present invention, the semiconductor device comprises: a semiconductor substrate; a gate region located above the semiconductor substrate; S/D regions located at both sides of the gate region and made of a stress material; wherein a concentrated stress region is formed between the gate region and the semiconductor substrate, and the concentrated stress region comprises an upper SOI layer adjacent to the gate region above, and a lower stress release layer adjacent to the semiconductor substrate below. The present invention applies to the manufacturing of a MOSFET.
摘要翻译：本发明公开了一种半导体器件及其制造方法，涉及半导体制造领域。根据本发明，半导体器件包括：半导体衬底; 位于半导体衬底上方的栅极区域; S / D区域位于栅极区域的两侧并由应力材料制成; 其中在所述栅极区域和所述半导体衬底之间形成集中应力区域，并且所述集中应力区域包括与所述栅极区域相邻的上部SOI层以及与所述半导体衬底相邻的较低应力释放层。本发明适用于MOSFET的制造。

43. 发明申请

US20110006371A1 INDUCING STRESS IN CMOS DEVICE 有权
标题翻译：在CMOS器件中产生应力
公开(公告)号：US20110006371A1
公开(公告)日：2011-01-13
申请号：US12500107
申请日：2009-07-09
申请人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/1203 , H01L29/7843 , H01L29/7848
摘要： A first aspect of the invention provides a method of forming a semiconductor device, the method comprising: providing a complimentary metal oxide semiconductor (CMOS) device including: a silicon substrate layer; a silicon dioxide layer thereover; and an n-type field effect transistor (NFET) gate having a first recessed source/drain trench and a p-type field effect transistor (PFET) gate having a second recessed source/drain trench, the NFET gate and the PFET gate located over the silicon dioxide layer; depositing a nitride stress liner in the first recessed source/drain trench and the second recessed source/drain trench; depositing an oxide layer over the nitride stress liner; placing the CMOS device on a handling wafer, wherein the oxide layer is closest to the handling wafer; removing the silicon substrate layer; etching the silicon dioxide layer to form an opening abutting a portion of a source/drain region, the source/drain region abutting one of the first recessed source/drain trench or the second recessed source/drain trench; and forming a contact in the opening.
摘要翻译：本发明的第一方面提供一种形成半导体器件的方法，所述方法包括：提供互补金属氧化物半导体（CMOS）器件，其包括：硅衬底层; 二氧化硅层; 和具有第一凹陷源极/漏极沟槽的n型场效应晶体管（NFET）栅极和具有第二凹陷源极/漏极沟槽的p型场效应晶体管（PFET）栅极，所述NFET栅极和PFET栅极位于二氧化硅层; 在第一凹陷源极/漏极沟槽和第二凹陷源极/漏极沟槽中沉积氮化物应力衬垫; 在氮化物应力衬垫上沉积氧化物层; 将CMOS器件放置在处理晶片上，其中氧化物层最靠近处理晶片; 去除硅衬底层; 蚀刻所述二氧化硅层以形成邻接所述源/漏区的一部分的开口，所述源极/漏极区邻接所述第一凹陷源极/漏极沟槽或所述第二凹陷源极/漏极沟槽中的一个; 并在开口中形成接触。

44. 发明授权

US09214400B2 Semiconductor device with back gate isolation regions and method for manufacturing the same 有权
标题翻译：具有背栅隔离区的半导体器件及其制造方法
公开(公告)号：US09214400B2
公开(公告)日：2015-12-15
申请号：US13504643
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed completely under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs. In addition to back gate isolation implemented by the shallow trench isolation between the adjacent MOSFETs, the adjacent MOSFETs are also isolated by means of PNPN junctions or NPNP junctions formed in the back gates and the back gate isolation regions. As a result, the semiconductor device has a better isolation effect, and thus the possibility of accidental breakdown of the semiconductor device is substantially reduced.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：SOI晶片，其包括半导体衬底，绝缘掩埋层和半导体层，其中绝缘掩埋层设置在半导体衬底上，并且半导体层设置在绝缘掩埋层上; 形成在SOI晶片中的相邻MOSFET，其中每个相邻的MOSFET包括形成在半导体衬底中的背栅和完全在后栅下形成的背栅隔离区; 和浅沟槽隔离，其中在相邻的MOSFET之间形成浅沟槽隔离以将相邻的MOSFET彼此隔离，其中在每个相邻MOSFET的背栅极和背栅极隔离区域之间形成PN结。根据本公开的实施例，在相邻MOSFET的背栅隔离区之间形成PN结。除了通过相邻MOSFET之间的浅沟槽隔离实现的背栅隔离之外，相邻的MOSFET也通过形成在后栅极和后栅极隔离区域中的PNPN结或NPNP结隔离。结果，半导体器件具有更好的隔离效果，从而显着降低了半导体器件意外击穿的可能性。

45. 发明授权

US09012272B2 MOSFET and method for manufacturing the same 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US09012272B2
公开(公告)日：2015-04-21
申请号：US13379444
申请日：2011-08-01
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/76 , H01L27/12 , H01L21/265 , H01L29/423 , H01L29/786
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/42384 , H01L29/78648
摘要： The present application discloses an MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first insulation buried layer disposed on the semiconductor substrate; a back gate formed in a first semiconductor layer which is disposed on the first insulation buried layer; a second insulation buried layer disposed on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is disposed on the second insulation buried layer; a gate disposed on the second semiconductor layer; and electric connections to the source/drain regions, the gate and the back gate, wherein the back gate comprises first back gate regions of a first conductivity type which are disposed under the source/drain regions and a second back gate region of a second conductivity type which is disposed under a channel region, the first back gate regions adjoins the second back gate region, the first conductivity type is opposite to the second conductivity type, and the electric connection to the back gate comprise a conductive via contacted with one of the first back gate regions. The MOSFET, of any conductivity type, can have adjustable threshold voltage and reduced leakage current via the back gate between the source/drain regions by using the back gate in the form of a PNP junction or an NPN junction.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET包括：半导体衬底; 设置在所述半导体基板上的第一绝缘埋层; 形成在第一绝缘掩埋层上的第一半导体层中形成的背栅; 设置在所述第一半导体层上的第二绝缘埋层; 源极/漏极区域，形成在第二绝缘掩埋层上的第二半导体层中; 设置在所述第二半导体层上的栅极; 以及与源极/漏极区域，栅极和背栅极的电连接，其中所述背栅极包括设置在所述源极/漏极区域下方的第一导电类型的第一后栅极区域和具有第二导电性的第二背栅极区域所述第一导电类型与所述第二导电类型相反，并且与所述第二导电类型的电连接包括与所述第二导电类型之一接触的导电通孔，第一个后门区域。任何导电类型的MOSFET可以通过使用PNP结或NPN结形式的背栅，通过源极/漏极区之间的背栅极具有可调节的阈值电压和减小的漏电流。

46. 发明申请

US20150076602A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150076602A1
公开(公告)日：2015-03-19
申请号：US14394802
申请日：2012-05-30
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/265 , H01L21/324 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7849 , H01L21/265 , H01L21/26506 , H01L21/2652 , H01L21/324 , H01L29/0649 , H01L29/66545 , H01L29/66583 , H01L29/66772 , H01L29/78654
摘要： A method for manufacturing a semiconductor structure, comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.
摘要翻译：一种制造半导体结构的方法，包括以下步骤：在SOI衬底上提供SOI衬底并形成栅极结构; 通过使用栅极结构作为掩模来注入离子以在半导体结构中引起应力，以形成位于栅极结构两侧的SOI衬底上的BOX层下方的应力诱导区域。还公开了根据上述方法制造的半导体结构。在本申请中公开的半导体结构及其制造方法在地层上形成应力诱导区域，其对半导体器件沟道提供有利的应力，有助于提高半导体器件的性能。

47. 发明授权

US08492842B2 Method for forming retrograded well for MOSFET 有权
标题翻译：用于形成MOSFET回流井的方法
公开(公告)号：US08492842B2
公开(公告)日：2013-07-23
申请号：US13429948
申请日：2012-03-26
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L27/12
CPC分类号： H01L21/187 , H01L21/6835 , H01L21/84 , H01L27/12 , H01L29/1083 , H01L2221/6835 , H01L2221/68368
摘要： A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.
摘要翻译：提供一种形成电气装置的方法，包括在SOI衬底的第一半导体层上形成至少一个半导体器件。形成接触至少一个半导体器件和第一半导体层的处理结构。去除第二半导体层和SOI衬底的电介质层的至少一部分以提供第一半导体层的基本暴露的表面。可以通过将掺杂剂通过第一半导体层的基本上暴露的表面注入从半导体层的基本暴露的表面延伸的半导体层的第一厚度来形成退化的阱，其中半导体层的剩余厚度基本上不含的回归井掺杂剂。退火井可以进行激光退火。

48. 发明申请

US20130049116A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130049116A1
公开(公告)日：2013-02-28
申请号：US13504643
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs. In addition to back gate isolation implemented by the shallow trench isolation between the adjacent MOSFETs, the adjacent MOSFETs are also isolated by means of PNPN junctions or NPNP junctions formed in the back gates and the back gate isolation regions. As a result, the semiconductor device has a better isolation effect, and thus the possibility of accidental breakdown of the semiconductor device is substantially reduced.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：SOI晶片，其包括半导体衬底，绝缘掩埋层和半导体层，其中绝缘掩埋层设置在半导体衬底上，并且半导体层设置在绝缘掩埋层上; 形成在SOI晶片中的相邻的MOSFET，其中每个相邻的MOSFET包括形成在半导体衬底中的背栅和形成在后栅下的背栅隔离区; 和浅沟槽隔离，其中在相邻的MOSFET之间形成浅沟槽隔离以将相邻的MOSFET彼此隔离，其中在每个相邻MOSFET的背栅极和背栅极隔离区域之间形成PN结。根据本公开的实施例，在相邻MOSFET的背栅隔离区之间形成PN结。除了通过相邻MOSFET之间的浅沟槽隔离实现的背栅隔离之外，相邻的MOSFET也通过形成在后栅极和后栅极隔离区域中的PNPN结或NPNP结隔离。结果，半导体器件具有更好的隔离效果，从而显着降低了半导体器件意外击穿的可能性。

49. 发明申请

US20120261759A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20120261759A1
公开(公告)日：2012-10-18
申请号：US13379081
申请日：2011-06-01
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/28123 , H01L21/76232 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/665 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device comprising: a semiconductor substrate; an STI embedded into the semiconductor substrate and having at least a semiconductor opening region; a channel region in the semiconductor opening region; a gate stack comprising a gate dielectric layer and a gate conductive layer and located above the channel region; and source/drain regions located on both sides of the channel region, and comprising first seed layers on opposite sides of the gate stack adjacent to the STI, wherein the upper surface of the STI is higher than or sufficiently closed to the upper surface of the gate dielectric layer. The semiconductor device and the method for manufacturing the same can enhance the stress of the channel region so as to improve device performance.
摘要翻译：一种半导体器件，包括：半导体衬底; STI嵌入到所述半导体衬底中并具有至少半导体开口区域; 半导体开口区域中的沟道区域; 栅极堆叠，其包括栅极电介质层和栅极导电层并且位于沟道区域上方; 以及位于沟道区两侧的源极/漏极区，并且包括邻近STI的栅堆叠相对侧上的第一晶种层，其中STI的上表面高于或充分地闭合到栅介质层。半导体器件及其制造方法可以增强沟道区的应力，从而提高器件性能。

50. 发明申请

US20120217583A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120217583A1
公开(公告)日：2012-08-30
申请号：US13144375
申请日：2011-02-24
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Qingqing Liang
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Qingqing Liang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/76224 , H01L21/28123 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A semiconductor structure and a method for forming the structure are provided. The semiconductor structure has a STI structure which has a top surface higher than or as high as that of source/drain stressors. A dummy gate and a spacer are added on the STI structure. The method comprises: providing a semiconductor substrate; embedding a STI structure in the semiconductor substrate in order to form isolated active areas; forming a gate stack on the active area, and forming a dummy gate on the STI structure; forming a first spacer on sidewalls of the dummy gate, wherein a part of the first spacer lands on the active area; and embedding source/drain stressors in the semiconductor substrate and at opposite sides of the gate stack, wherein the top surface of the STI structure is higher than or as high as that of the source/drain stressor.
摘要翻译：提供半导体结构和形成该结构的方法。半导体结构具有STI结构，其具有高于或高于源/漏应力源的顶表面。在STI结构上添加了虚拟栅极和间隔物。该方法包括：提供半导体衬底; 在所述半导体衬底中嵌入STI结构以形成隔离的有源区; 在有源区上形成栅极叠层，在STI结构上形成一个虚拟栅极; 在所述虚拟栅极的侧壁上形成第一间隔物，其中所述第一隔离物的一部分在有源区域上着陆; 并且将源极/漏极应力源嵌入在栅极叠层的半导体衬底和相对侧，其中STI结构的顶表面高于源极/漏极应力源的顶表面。

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