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41. 发明授权

US08313979B2 Phase change memory cell having vertical channel access transistor 有权
标题翻译：具有垂直沟道存取晶体管的相变存储单元
公开(公告)号：US08313979B2
公开(公告)日：2012-11-20
申请号：US13110197
申请日：2011-05-18
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.
摘要翻译：一种器件包括具有第一区域和第二区域的衬底。第一区域包括在衬底内具有水平沟道区的第一场效应晶体管，覆盖在水平沟道区上的栅极和覆盖第一场效应晶体管的栅极的第一电介质。衬底的第二区域包括第二场效应晶体管，其包括延伸穿过第一电介质以接触衬底的第一端子，覆盖第一端子并具有顶表面的第二端子和分离第一和第二端子的垂直沟道区域。第二场效应晶体管还包括在第一电介质上并且与垂直沟道区相邻的栅极，栅极具有与第二端子的顶表面共面的顶表面。

42. 发明授权

US08143612B2 Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing 有权
标题翻译：具有自对准，自会聚底电极的通孔阵列中的相变存储单元及其制造方法
公开(公告)号：US08143612B2
公开(公告)日：2012-03-27
申请号：US12621000
申请日：2009-11-18
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： H01L29/06
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/122 , H01L45/1253 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.
摘要翻译：通过在触点阵列上形成分离层，在分离层上形成隔离层并使用光刻工艺在隔离层中形成阵列的存储元件开口来制造“蘑菇”型相变存储器单元的阵列。通过补偿由光刻工艺产生的存储元件开口的尺寸变化的过程，在存储元件开口内形成蚀刻掩模。蚀刻掩模用于蚀刻穿过分离层以限定电极开口的阵列。电极材料沉积在电极开口内; 并且存储元件形成在存储元件开口内。存储元件和底部电极是自对准的。

43. 发明授权

US08030635B2 Polysilicon plug bipolar transistor for phase change memory 有权
标题翻译：用于相变存储器的多晶硅插头双极晶体管
公开(公告)号：US08030635B2
公开(公告)日：2011-10-04
申请号：US12353219
申请日：2009-01-13
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung Hon Lam
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung Hon Lam
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , G11C13/0004 , H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.
摘要翻译：本文描述了存储器件和制造方法。本文描述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极与多个字线中的对应字线接触以限定pn结。双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

44. 发明授权

US07968876B2 Phase change memory cell having vertical channel access transistor 有权
标题翻译：具有垂直沟道存取晶体管的相变存储单元
公开(公告)号：US07968876B2
公开(公告)日：2011-06-28
申请号：US12471301
申请日：2009-05-22
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices are described along with methods for manufacturing. A device as described herein includes a substrate having a first region and a second region. The first region comprises a first field effect transistor comprising first and second doped regions separated by a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. A second dielectric separates the gate of the second field effect transistor from the vertical channel region.
摘要翻译：描述存储器件以及制造方法。如本文所述的器件包括具有第一区域和第二区域的衬底。第一区域包括第一场效应晶体管，其包括由衬底内的水平沟道区域分隔的第一和第二掺杂区域，覆盖在水平沟道区域上的栅极和覆盖第一场效应晶体管的栅极的第一电介质。衬底的第二区域包括第二场效应晶体管，其包括延伸穿过第一电介质以接触衬底的第一端子，覆盖第一端子并具有顶表面的第二端子和分离第一和第二端子的垂直沟道区域。第二场效应晶体管还包括在第一电介质上并且与垂直沟道区相邻的栅极，栅极具有与第二端子的顶表面共面的顶表面。第二电介质将第二场效应晶体管的栅极与垂直沟道区分开。

45. 发明授权

US07755935B2 Block erase for phase change memory 失效
标题翻译：块擦除相变存储器
公开(公告)号：US07755935B2
公开(公告)日：2010-07-13
申请号：US11828717
申请日：2007-07-26
申请人： Chung Hon Lam , Hsiang-Lan Lung
发明人： Chung Hon Lam , Hsiang-Lan Lung
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/74
摘要： An embodiment of our invention includes a method of programming at least one phase change memory block, the at least one block comprising at least one phase change memory cell, the at least one cell comprising at least one phase change material. The method includes the steps of transitioning all cells within the at least one block to a first state and, after all cells within the at least one block have been transitioned to the first state, transitioning at least one cell within the at least one block to at least a second state. Transitioning a cell to the at least second state is faster than transitioning a cell to the first state. At least the step of transitioning all cells within the at least one block to a first state may include transitioning all cells within the at least one block in a substantially simultaneous manner.
摘要翻译：本发明的实施例包括编程至少一个相变存储器块的方法，所述至少一个块包括至少一个相变存储器单元，所述至少一个单元包括至少一个相变材料。该方法包括以下步骤：将至少一个块内的所有小区转换到第一状态，并且在至少一个块内的所有小区已经转变到第一状态之后，将至少一个块内的至少一个小区转换为至少第二状态。将单元转换到至少第二状态比将单元转换到第一状态更快。至少将至少一个块内的所有小区转换到第一状态的步骤可以包括以基本上同时的方式转换至少一个块内的所有小区。

46. 发明授权

US07729161B2 Phase change memory with dual word lines and source lines and method of operating same 有权
标题翻译：具有双字线和源极线的相变存储器及其操作方法
公开(公告)号：US07729161B2
公开(公告)日：2010-06-01
申请号：US11833143
申请日：2007-08-02
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C8/08 , G11C8/14 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/74 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the first word line conductor to establish a current path from the bit line through the memory cell to a source line through the first access device, and to access the memory cell for operations to reset the memory cell using both the first and second access devices to establish a current path from the bit line through the memory cell to two source lines.
摘要翻译：相变存储器件包括存储单元，第一字线导体和第二字线导体，以及分别响应于第一和第二字线导体的第一和第二存取器件。控制电路被布置为仅使用第一字线导体访问存储器单元用于读取操作，以建立从位线到存储器单元到通过第一存取设备到源极线的电流路径，以及访问存储器单元以进行操作使用第一和第二接入设备来复位存储器单元以建立从位线到存储器单元到两条源极线的电流路径。

47. 发明申请

US20090185411A1 INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS 审中-公开
标题翻译：集成电路，包括二极管记忆体
公开(公告)号：US20090185411A1
公开(公告)日：2009-07-23
申请号：US12017581
申请日：2008-01-22
申请人： Thomas Happ , Chung Hon Lam , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
发明人： Thomas Happ , Chung Hon Lam , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： H01L27/24 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2213/71 , G11C2213/72
摘要： The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.
摘要翻译：集成电路包括耦合到第一金属线的第一金属线和第一二极管。集成电路包括耦合到第一二极管的第一电阻率变化材料和耦合到第一电阻率变化材料的第二金属线。

48. 发明授权

US07488967B2 Structure for confining the switching current in phase memory (PCM) cells 失效
标题翻译：将开关电流限制在相位存储器（PCM）单元中的结构
公开(公告)号：US07488967B2
公开(公告)日：2009-02-10
申请号：US11100312
申请日：2005-04-06
申请人： Geoffrey W. Burr , Chung Hon Lam , Simone Raoux , Stephen M. Rossnagel , Alejandro G. Schrott , Jonathan Z. Sun , Hemantha K. Wickramasinghe
发明人： Geoffrey W. Burr , Chung Hon Lam , Simone Raoux , Stephen M. Rossnagel , Alejandro G. Schrott , Jonathan Z. Sun , Hemantha K. Wickramasinghe
IPC分类号： H01L29/02
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： Disclosed are a phase change memory cell and a method of forming the memory cell. The memory cell comprises a main body of phase change material connected directly to a bottom contact and via a narrow channel of phase change material to a top contact. The channel is tapered from the top contact towards the main body. A minimum width of the channel has a less than minimum lithographic dimension and is narrower than a width of the main body. Therefore, the channel provides a confined region for the switching current path and restricts phase changing to within the channel. In addition an embodiment of the memory cell isolates the main body of phase change material by providing a space between the phase change material and the cell walls. The space allows the phase change material to expand and contract and also limits heat dissipation.
摘要翻译：公开了相变存储单元和形成存储单元的方法。存储单元包括相变材料的主体，其直接连接到底部触点，并经由相位改变材料的窄通道连接到顶部触点。通道从顶部触点向主体逐渐变细。通道的最小宽度具有小于最小光刻尺寸，并且窄于主体的宽度。因此，该通道为开关电流路径提供一个限制区域，并将相位变化限制在通道内。此外，存储器单元的实施例通过在相变材料和单元壁之间提供空间来隔离相变材料的主体。该空间允许相变材料膨胀和收缩，并且还限制了散热。

49. 发明授权

US08589320B2 Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks 有权
标题翻译：将二极管配置中的FET和可变电阻材料连接到神经元电路块的结的区域有效的神经元系统
公开(公告)号：US08589320B2
公开(公告)日：2013-11-19
申请号：US13548532
申请日：2012-07-13
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06E1/00
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic system includes a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks. The plurality of synapse blocks includes a plurality of neuromorphic circuits. Each neuromorphic circuit includes a field effect transistor in a diode configuration electrically connected to variable resistance material, where the variable resistance material provides a programmable resistance value. Each neuromorphic circuit also includes a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks, and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks.
摘要翻译：神经元系统包括电连接到多个神经元电路块的多个突触块。多个突触块包括多个神经形态电路。每个神经形态电路包括电连接到可变电阻材料的二极管配置中的场效应晶体管，其中可变电阻材料提供可编程电阻值。每个神经形态电路还包括电连接到可变电阻材料的第一结和一个或多个神经元电路块的输出，以及电连接到场效应晶体管的第二结和一个或多个神经元电路的输入块。

50. 发明授权

US08311965B2 Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material 有权
标题翻译：使用场效应晶体管（FET）和可变电阻材料的区域效率的神经元电路
公开(公告)号：US08311965B2
公开(公告)日：2012-11-13
申请号：US12620624
申请日：2009-11-18
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06F17/00
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic circuit includes a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor. The neuromorphic circuit also includes a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor. The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value. The neuromorphic circuit additionally includes a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit, and a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit.
摘要翻译：神经形态电路包括在第一二极管配置中建立第一场效应晶体管的第一栅极和第一漏极之间的电连接的第一场效应晶体管。神经形态电路还包括在第二二极管配置中建立第二场效应晶体管的第二栅极和第二漏极之间的电连接的第二场效应晶体管。神经形态电路还包括电连接到第一漏极和第二漏极的可变电阻材料，其中可变电阻材料提供可编程电阻值。神经形态电路还包括电连接到可变电阻材料并且提供到神经元电路的输出的第一连接点的第一结，以及电连接到可变电阻材料并且提供第二连接点到第二连接点的第二连接点神经元电路。

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