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41. 发明授权

US6087710A Semiconductor device having self-aligned contacts 失效
标题翻译：具有自对准触点的半导体器件
公开(公告)号：US6087710A
公开(公告)日：2000-07-11
申请号：US687624
申请日：1996-07-26
申请人： Takahisa Eimori , Hiroshi Kimura
发明人： Takahisa Eimori , Hiroshi Kimura
IPC分类号： H01L23/522 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L23/48
CPC分类号： H01L27/10844 , H01L21/76897
摘要： In a peripheral circuit region requiring a conductive path between layers at the periphery of a memory cell array region, a conductive path is provided, after removing a silicon nitride film used for self-alignment contact from the area of the contacting portion of a conductor, by forming an interlayer oxide film on the conductor and providing an opening through the interlayer oxide film. Alternatively, a conductive path is provided, after forming the interlayer oxide film on the silicon nitride film used for self-alignment contact, by forming an opening throughout the interlayer oxide film and silicon nitride film.
摘要翻译：在需要在存储单元阵列区域的外围的层之间的导电路径的外围电路区域中，在从导体的接触部分的区域去除用于自对准接触的氮化硅膜之后，提供导电路径，通过在导体上形成层间氧化膜，并提供通过层间氧化膜的开口。或者，通过在整个层间氧化膜和氮化硅膜上形成开口，在用于自对准接触的氮化硅膜上形成层间氧化膜之后，提供导电路径。

42. 发明授权

US5637899A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5637899A
公开(公告)日：1997-06-10
申请号：US640638
申请日：1996-05-01
申请人： Takahisa Eimori , Toshiyuki Oashi , Kenichi Shimomura
发明人： Takahisa Eimori , Toshiyuki Oashi , Kenichi Shimomura
IPC分类号： H01L21/762 , H01L21/76 , H01L21/822 , H01L27/04 , H01L27/12 , H01L29/423 , H01L29/786 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/78645 , H01L27/1203 , H01L29/42384 , H01L29/78612
摘要： An SOI-MOS transistor structure is obtained which enables prevention of a substrate floating effect, reduction of the gate capacity and the contact resistance, and connection of two or more transistors in series. A semiconductor device including this transistor includes a pair of n.sup.+ type source/drain regions and a p.sup.+ type channel potential fixing region formed by dividing an active region by a first wiring and a second wiring, and a third wiring and a fourth wiring extending from respective side portions of the wirings. Since holes stored in an effective channel region flow in the p.sup.+ type channel potential fixing region, the substrate flowing effect can be prevented. Since one region of the pair of n.sup.+ type source/drain regions is wider than the other region, the contact resistance can be decreased. Further, since the gate wirings are not connected to each other, transistors can be connected in series.
摘要翻译：可以获得SOI-MOS晶体管结构，能够防止衬底浮置效应，栅极容量和接触电阻的降低以及两个或更多个串联的晶体管的连接。包括该晶体管的半导体器件包括一对n +型源极/漏极区域和通过用第一布线和第二布线分割有源区域形成的p +型沟道电位固定区域，以及从相应的第一布线和第二布线延伸的第三布线和第四布线配线的侧面部分。由于存储在有效沟道区中的空穴在p +型沟道电位固定区中流动，所以可以防止衬底流动效应。由于一对n +型源极/漏极区域的一个区域比另一个区域宽，所以可以降低接触电阻。此外，由于栅极布线彼此不连接，所以可以串联连接晶体管。

43. 发明授权

US5442212A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5442212A
公开(公告)日：1995-08-15
申请号：US292303
申请日：1994-08-18
申请人： Takahisa Eimori
发明人： Takahisa Eimori
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/68
CPC分类号： H01L27/10808
摘要： In a semiconductor memory device, pitch of bit lines is made larger than pitch of word lines, and a storage node contact is positioned in each rectangular area surrounded by the bit lines and the word lines. The distance between centers of adjacent storage node contacts and the distance between centers of a bit line contact and an adjacent storage node contact are both made larger than the pitch of word lines. By this structure, planar area per unit memory cell can be increased, registration margin between the storage node and the storage node contact can be enlarged, short-circuit between the bit line and the storage node contact is prevented, and thus a memory cell structure of high production yield and high reliability can be realized.
摘要翻译：在半导体存储器件中，位线的间距大于字线的间距，并且存储节点接点位于由位线和字线包围的每个矩形区域中。相邻存储节点触点的中心之间的距离以及位线接触的中心与相邻的存储节点触点之间的距离都大于字线的间距。通过这种结构，可以增加每单位存储单元的平面面积，可以扩大存储节点与存储节点接触点之间的配准余量，从而防止位线与存储节点接触之间的短路，从而存储单元结构可以实现高产量和高可靠性。

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