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    • 43. 发明授权
    • Band-to-band resonant tunneling transistor
    • 带对带谐振隧道晶体管
    • US5489785A
    • 1996-02-06
    • US209789
    • 1994-03-11
    • Saied N. TehraniJun ShenHerbert GoronkinXiaodong T. Zhu
    • Saied N. TehraniJun ShenHerbert GoronkinXiaodong T. Zhu
    • H01L29/68H01L29/06H01L29/205H01L29/737H01L27/12
    • H01L29/7376B82Y10/00
    • A band-to-band resonant tunneling transistor including GaSb and InAs resonant tunneling layers separated by a thin barrier layer and a second InAs layer separated from the GaSb layer by another thin barrier layer. A terminal on the InAs resonant tunneling layer and a terminal on the second InAs layer. Leakage current reduction layers are positioned on the second InAs layer with a bias terminal positioned thereon. The InAs resonant tunneling layer has a plurality of quantized states which are misaligned with the ground state of the GaSb layer in a quiescent state, each of the quantized states of the InAs resonant tunneling layer are movable into alignment with the ground state of the GaSb layer to provide current flow through the transistor with the application of a specific potential to the terminal on the second InAs layer.
    • 包括GaSb和InAs谐振隧道层的带对带谐振隧穿晶体管,其由薄的阻挡层和由另一个薄的阻挡层与GaSb层分离的第二InAs层隔开。 InAs谐振隧穿层上的一个端子和第二个InAs层上的一个端子。 漏电流减少层位于第二InAs层上,偏置端子位于其上。 InAs谐振隧穿层具有与处于静止状态的GaSb层的基态不对准的多个量化状态,InAs谐振隧穿层的每个量子化状态可移动地与GaSb层的基态对准 以通过向第二InAs层上的端子施加特定电位来提供流过晶体管的电流。
    • 45. 发明授权
    • Method of fabricating a complementary heterojunction FET
    • 制造互补异质结FET的方法
    • US5427965A
    • 1995-06-27
    • US262292
    • 1994-06-20
    • Saied N. TehraniX. T. ZhuHerbert GoronkinJun Shen
    • Saied N. TehraniX. T. ZhuHerbert GoronkinJun Shen
    • H01L29/80H01L27/06H01L27/092H01L27/095H01L21/265H01L21/20
    • H01L27/0605H01L27/092Y10S148/015Y10S148/072Y10S148/16
    • A heterojunction device including a first semiconductive layer on a substrate, a barrier layer on the first layer, a second semiconductive layer on the barrier layer and a multi-layer cap, on the second semiconductive layer. First and second gates positioned on layers of the cap to define first and second transistors, with the cap layers being selected and etched to pin the Fermi level in a first transistor conduction channel in the second semiconductive layer such that the number of carriers in the first conduction channel are substantially less than the number of carriers in surrounding portions of the second semiconductive layer and the Fermi level in a second transistor conduction channel in the first semiconductive layer such that the number of carriers in the second conduction channel are substantially less than the number of carriers in surrounding portions of the first semiconductive layer.
    • 一种异质结装置,在第二半导体层上包括衬底上的第一半导体层,第一层上的阻挡层,阻挡层上的第二半导体层和多层帽。 位于盖的层上的第一和第二栅极限定第一和第二晶体管,其中盖层被选择和蚀刻以在第二半导体层中的第一晶体管导通通道中引导费米能级,使得第一和第二晶体管中的载流子数目 传导通道基本上小于第一半导体层中的第二半导体层的周围部分中的载流子数量和第二晶体管传导通道中的费米能级数,使得第二导电通道中的载流子数目基本上小于数量 在第一半导体层的周围部分的载体。