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41. 发明授权

US07349677B2 Hardware efficient RF transceiver I/Q imbalance compensation based upon taylor approximation 有权
标题翻译：基于泰勒近似的硬件高效RF收发器I / Q不平衡补偿
公开(公告)号：US07349677B2
公开(公告)日：2008-03-25
申请号：US10821057
申请日：2004-04-08
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H04B1/12
CPC分类号： H04L27/0014 , H04L2027/0016 , H04L2027/0018 , H04L2027/0024
摘要： Radio transceiver circuitry includes I/Q imbalance compensation logic within at least one of a digital modulator or a digital demodulator, depending upon whether the I/Q imbalance compensation block is compensating for I/Q imbalance in a transmit path or in a receive path. For a transmitter, a digital processor includes a baseband processor that produces transmit data (digital data) for transmission to a digital modulator that includes an I/Q imbalance compensation logic. The digital modulator, which may modulate in any known modulation scheme, produces in-phase and quadrature phase components that have been pre-compensated for I/Q imbalance that is introduced by downstream analog circuitry in the transmit path. In at least one embodiment of the invention, a “steepest descent” algorithm for finding optimal values of I/Q imbalance compensation parameters based upon a small number of image rejection measurements are used.
摘要翻译：无线电收发器电路包括数字调制器或数字解调器中的至少一个中的I / Q不平衡补偿逻辑，这取决于I / Q不平衡补偿块是否补偿发送路径或接收路径中的I / Q不平衡。对于发射机，数字处理器包括基带处理器，其产生用于传输到包括I / Q不平衡补偿逻辑的数字调制器的发射数据（数字数据）。可以在任何已知调制方案中调制的数字调制器产生已被预补偿由发射路径中的下游模拟电路引入的I / Q不平衡的同相和正交相分量。在本发明的至少一个实施例中，使用基于少量图像抑制测量来找到I / Q不平衡补偿参数的最佳值的“最速下降”算法。

42. 发明授权

US07215703B2 Digital calculation received signal strength indication 有权
标题翻译：数字计算接收信号强度指示
公开(公告)号：US07215703B2
公开(公告)日：2007-05-08
申请号：US10367492
申请日：2003-02-14
申请人： Henrik T. Jensen , Brima B. Ibrahim
发明人： Henrik T. Jensen , Brima B. Ibrahim
IPC分类号： H04B17/00
CPC分类号： H04B17/318 , H04B17/21
摘要： Digital calculation of an RSSI value begins by digitally calculating a magnitude of a signal (e.g., a received RF signal or representation thereof). The process then continues by filtering the magnitude of the signal to produce a filtered magnitude signal. The process then continues by determining a coarse RSSI value of the filtered magnitude signal, wherein the coarse RSSI value indicates a sliding window of RSSI values. Once the coarse RSSI value is obtained, the process continues by determining a fine RSSI value within the sliding window of RSSI values. The process concludes by summing the fine RSSI value with the coarse RSSI value to produce a digital RSSI value.
摘要翻译：通过数字计算信号的幅度（例如，接收的RF信号或其表示）开始RSSI值的数字计算。然后，该过程通过对信号的幅度进行滤波来继续以产生经滤波的幅度信号。然后，该过程通过确定滤波的幅度信号的粗略RSSI值继续，其中粗略RSSI值表示RSSI值的滑动窗口。一旦获得了粗糙的RSSI值，则通过确定RSSI值的滑动窗口内的精细RSSI值来继续该过程。该过程通过将精细RSSI值与粗RSSI值相加来产生数字RSSI值。

43. 发明授权

US07027780B2 Technique for improving modulation performance of translational loop RF transmitters 失效
公开(公告)号：US07027780B2
公开(公告)日：2006-04-11
申请号：US10676221
申请日：2003-09-30
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H04B1/02
CPC分类号： H04L27/368
摘要： A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps: a magnitude equalizer in the baseband processor pre-distorts the amplitude of the transmit signal according to the inverse of the PLL signal filter magnitude response, and a group delay equalizer linearizes the phase response of the entire transmitter chain, i.e., pre-distorts the transmit signal such that the combined phase response of magnitude equalizer, group delay equalizer, and PLL signal filter is linear. With such pre-distortion, a loop filter is provided for with component values that define a relatively small bandwidth for the loop filter to filter spurious tones that result from an IF reference feedthrough to a voltage controlled oscillator of the translational loop.

44. 发明授权

US06941116B2 Linearization technique for phase locked loops employing differential charge pump circuitry 失效
标题翻译：采用差分电荷泵电路的锁相环线性化技术
公开(公告)号：US06941116B2
公开(公告)日：2005-09-06
申请号：US10306040
申请日：2002-11-27
申请人： Henrik T. Jensen , Michael Kappes
发明人： Henrik T. Jensen , Michael Kappes
IPC分类号： H01Q1/24 , H03L7/089 , H03L7/197 , H04B1/40 , H03D3/24 , H04B7/00
CPC分类号： H03L7/0896 , H01Q1/246 , H03L7/1974
摘要： A differential linear fractional N-synthesizer includes a phase and frequency detection module, a linearized charge pump, a low pass filter, a voltage controlled oscillator, and a fractional N divider feedback. The phase and frequency detection module is operably coupled to produce a differential charge-up signal, a differential charge-down signal, or a differential off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The feedback oscillation is generated by the fractional N divider feedback, which divides an output oscillation by a divider value to produce the feedback oscillation. The linearized charge pump includes a 1st current source, a 2nd current source and a modulation module. In response to the differential off signal, the modulation module produces a modulated differential off signal that causes the 1st and 2nd current sources to produce a zero current signal in an alternating fashion. The low pass filter is operably coupled to attenuate the high frequency signal components produced by the modulation module of the linearized charge pump and to pass the positive, negative or zero current signals to produce a filtered signal. The voltage control oscillator produces the output oscillation based on the filtered signal.
摘要翻译：差分线性分数N合成器包括相位和频率检测模块，线性化电荷泵，低通滤波器，压控振荡器和分数N分频器反馈。相位和频率检测模块可操作地耦合以产生基于参考振荡和反馈振荡之间的相位和/或频率差的差分充电信号，差分放电信号或差分关断信号。反馈振荡由分数N分频器反馈产生，其将输出振荡除以分频器值以产生反馈振荡。线性化电荷泵包括电流源1，电流源2和调制模块2。响应于差分关闭信号，调制模块产生调制的差分关断信号，使得第一和第二和第二电流源在交替地产生零电流信号时尚。低通滤波器可操作地耦合以衰减由线性化电荷泵的调制模块产生的高频信号分量，并传递正，负或零电流信号以产生滤波信号。电压控制振荡器基于滤波信号产生输出振荡。

45. 发明授权

US06362762B1 Multiple mode analog-to-digital converter employing a single quantizer 有权
标题翻译：采用单个量化器的多模式模数转换器
公开(公告)号：US06362762B1
公开(公告)日：2002-03-26
申请号：US09645072
申请日：2000-08-23
申请人： Henrik T. Jensen , Gopal Raghavan
发明人： Henrik T. Jensen , Gopal Raghavan
IPC分类号： H03M300
CPC分类号： H03M3/396 , H03M3/428 , H03M3/448 , H03M3/454
摘要： Several delta-sigma modulator circuits and a single quantizer provide analog-to-digital conversion for multiple frequency bands. A wideband mode is provided by coupling an analog signal to be digitized directly to a quantizer. Narrowband modes are provided by switching the analog signal to be digitized into one of several delta-sigma modulator circuits. Noise shaping and filtering by the delta-sigma modulator circuits result in improved signal-to-noise-and-distortion performance and increased resolution. Performance is further enhanced by feeding back multiple bits output by the quantizer to the delta-sigma modulator circuits. The delta-sigma modulator circuits can be either continuous time or discrete time delta sigma modulators.
摘要翻译：几个Δ-Σ调制器电路和单个量化器为多个频带提供模数转换。通过将要直接数字化的模拟信号耦合到量化器来提供宽带模式。通过将要数字化的模拟信号切换成几个Δ-Σ调制器电路之一来提供窄带模式。由Δ-Σ调制器电路进行的噪声整形和滤波导致改善的信噪比和失真性能并提高分辨率。通过将由量化器输出的多个比特反馈到Δ-Σ调制器电路，进一步增强了性能。 Δ-Σ调制器电路可以是连续时间或离散时间ΔΣ调制器。

46. 发明授权

US08296346B2 Channel-select decimation filter with programmable bandwidth 有权
标题翻译：具有可编程带宽的通道选择抽取滤波器
公开(公告)号：US08296346B2
公开(公告)日：2012-10-23
申请号：US12690532
申请日：2010-01-20
申请人： Henrik T. Jensen , Brima B. Ibrahim
发明人： Henrik T. Jensen , Brima B. Ibrahim
IPC分类号： G06F17/17 , G06F17/10
CPC分类号： H04L27/38 , H03H17/0664 , H03H17/0671
摘要： A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.
摘要翻译：能够在多个带宽模式下工作的频道选择抽取滤波器包括第一低通滤波器级，可变增益级，减法模块，第二低通滤波级和下采样模块。第一低通滤波器级包括用于滤波输入信号以产生第一低通滤波信号的第一可编程延迟模块。可变增益级将可编程增益应用于输入信号以产生增益的输入信号。减法模块从增益输入信号中减去第一低通滤波信号，以产生第一级信号。第二低通滤波器级包括用于对第一级信号进行滤波以产生通道选择信号的第二可编程延迟模块。第一可编程延迟模块，第二可编程延迟模块和可编程增益被编程以实现多种带宽模式之一。

47. 发明申请

US20100120387A1 CHANNEL-SELECT DECIMATION FILTER WITH PROGRAMMABLE BANDWIDTH 有权
标题翻译：具有可编程带宽的通道选择滤波器
公开(公告)号：US20100120387A1
公开(公告)日：2010-05-13
申请号：US12690532
申请日：2010-01-20
申请人： Henrik T. Jensen , Brima B. Ibrahim
发明人： Henrik T. Jensen , Brima B. Ibrahim
IPC分类号： H04B1/16 , H03H7/00 , H04B1/18
CPC分类号： H04L27/38 , H03H17/0664 , H03H17/0671
摘要： A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.
摘要翻译：能够在多个带宽模式下工作的频道选择抽取滤波器包括第一低通滤波器级，可变增益级，减法模块，第二低通滤波级和下采样模块。第一低通滤波器级包括用于滤波输入信号以产生第一低通滤波信号的第一可编程延迟模块。可变增益级将可编程增益应用于输入信号以产生增益的输入信号。减法模块从增益输入信号中减去第一低通滤波信号，以产生第一级信号。第二低通滤波器级包括用于对第一级信号进行滤波以产生通道选择信号的第二可编程延迟模块。第一可编程延迟模块，第二可编程延迟模块和可编程增益被编程以实现多种带宽模式之一。

48. 发明申请

US20090268847A1 PHASE LOCKED LOOP MODULATOR CALIBRATION TECHNIQUES 有权
标题翻译：相位锁定调制器校准技术
公开(公告)号：US20090268847A1
公开(公告)日：2009-10-29
申请号：US12436033
申请日：2009-05-05
申请人： Henrik T. Jensen , Hea Joung Kim
发明人： Henrik T. Jensen , Hea Joung Kim
IPC分类号： H04L27/12 , H04B1/04
CPC分类号： H03C3/0991 , H03L7/0898
摘要： A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.
摘要翻译：通过确定锁相环的压控振荡器的增益偏移开始校准锁相环的方法。然后通过基于增益偏移来调节锁相环的电荷泵的电流来继续处理。

49. 发明授权

US07471737B2 Hardware efficient FSK demodulator 失效
标题翻译：硬件高效的FSK解调器
公开(公告)号：US07471737B2
公开(公告)日：2008-12-30
申请号：US11015162
申请日：2004-12-17
申请人： Henrik T. Jensen , Paul Anthony Lettieri
发明人： Henrik T. Jensen , Paul Anthony Lettieri
IPC分类号： H03C3/00 , H04L25/03
CPC分类号： H04L27/368
摘要： A radio frequency (RF) transmitter includes a digital radio processor and a baseband processor. A complex analog-to-digital converter (ADC) within the radio processor provides an analog interface to the baseband processor to receive an analog complex modulated baseband signal and convert the analog complex modulated baseband signal to a digital complex modulated baseband signal. A demodulator within the radio processor demodulates the digital complex modulated baseband signal to recreate the original transmit digital data as a demodulated digital signal. The demodulated digital signal is processed by a digital processor in the radio processor to mitigate the effects of various imperfections in the radio processor circuitry.
摘要翻译：射频（RF）发射机包括数字无线电处理器和基带处理器。无线电处理器内的复数模数转换器（ADC）为基带处理器提供模拟接口，以接收模拟复调制基带信号，并将模拟复调制基带信号转换为数字复调制基带信号。无线电处理器内的解调器解调数字复调制基带信号，以重构原始发射数字数据作为解调数字信号。解调的数字信号由无线电处理器中的数字处理器处理以减轻无线电处理器电路中各种缺陷的影响。

50. 发明授权

US07397863B2 Implementation technique for linear phase equalization in multi-mode RF transmitters 失效
标题翻译：多模射频发射机线性相位均衡的实现技术
公开(公告)号：US07397863B2
公开(公告)日：2008-07-08
申请号：US10954911
申请日：2004-09-30
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H04L25/49 , H04L7/00
CPC分类号： H04B1/0475 , H04L25/03343
摘要： The present invention implements an architecture that changes the sequence of digital processing so that equalization occurs prior to phase accumulation. A phase differentiator receives an envelope path phase signal to produce a differentiated phase signal to an equalizer. The transfer function of the phase differentiator is implemented so that it cancels, except for a one-cycle delay, the transfer function of the phase accumulator. This cancellation substantially eliminates accumulation of the envelop path phase signal. Additionally, a dither signal added to the quantization nodes in the equalizers shifts the spectral content of the quantization noise such that the phase accumulator sees the quantization noise as zero mean white noise. Implemented as one of a rounding or flooring quantizer, biquad filters in the equalizers round or truncate the equalizer output to a minimal bit width based on a desired output phase error.
摘要翻译：本发明实现了改变数字处理序列以使相位累积之前发生均衡的架构。相位微分器接收包络线路相位信号以产生到均衡器的微分相位信号。实现相位微分器的传递函数，使得相位累加器的传递函数除了一个周期的延迟之外取消。该消除基本上消除了包络路径相位信号的累积。另外，加到均衡器中的量化节点的抖动信号将量化噪声的频谱内容移位，使得相位累加器将量化噪声视为零平均白噪声。实现为舍入或地板量化器之一，均衡器中的二进制滤波器基于期望的输出相位误差将均衡器输出舍入或截断到最小位宽度。

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