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41. 发明申请

US20090194736A1 Nanosized nickel-doped carbon nanotubes for hydrogen storage and production method thereof 审中-公开
标题翻译：用于氢存储的纳米镍掺杂碳纳米管及其制备方法
公开(公告)号：US20090194736A1
公开(公告)日：2009-08-06
申请号：US11396910
申请日：2006-04-04
申请人： Jai-Young Lee , Jeung-Ku Kang , Hyun-Seok Kim , Kyu-Sung Han , Min-Sang Song , Ho Lee , Jin-Ho Kim
发明人： Jai-Young Lee , Jeung-Ku Kang , Hyun-Seok Kim , Kyu-Sung Han , Min-Sang Song , Ho Lee , Jin-Ho Kim
IPC分类号： C09K3/00 , B01J13/02
CPC分类号： H01M8/04216 , B01J20/0225 , B01J20/20 , B01J20/205 , B01J20/3204 , B01J20/3236 , B01J20/3295 , B82Y30/00 , B82Y40/00 , C01B3/0021 , C01B32/162 , C01B32/168 , F17C11/005 , H01M8/0612 , Y02E60/321 , Y02E60/325
摘要： Disclosed herein is a method of doping nanosized nickel (Ni) on the surface of carbon nanotubes to improve the hydrogen storage capacity of the carbon nanotubes. The method comprises: sonicating carbon nanotube samples produced by vapor deposition, in sulfuric acid solution, followed by filtration to remove a metal catalyst from the carbon nanotube samples; and doping the carbon nanotube samples in liquid phase solution, followed by drying and reduction, so as to dope nanosized nickel on the surface of the carbon nanotubes.
摘要翻译：本文公开了在纳米碳管表面掺杂纳米尺寸镍（Ni）以提高碳纳米管的储氢能力的方法。该方法包括：在硫酸溶液中超声处理气相沉积产生的碳纳米管样品，然后过滤以从碳纳米管样品中除去金属催化剂; 并将碳纳米管样品掺杂在液相中，然后进行干燥和还原，从而将纳米尺寸的镍掺杂在碳纳米管的表面上。

42. 发明授权

US07511333B2 Nonvolatile memory cell with multiple floating gates and a connection region in the channel 有权
标题翻译：具有多个浮动栅极和通道中的连接区域的非易失性存储单元
公开(公告)号：US07511333B2
公开(公告)日：2009-03-31
申请号：US11246447
申请日：2005-10-06
申请人： Yue-Song He , Chung Wai Leung , Jin-Ho Kim , Kwok Kwok Ng
发明人： Yue-Song He , Chung Wai Leung , Jin-Ho Kim , Kwok Kwok Ng
IPC分类号： H01L27/115 , H01L29/66
CPC分类号： H01L29/42336 , G11C16/0458 , G11C16/0491 , H01L27/115 , H01L27/11521
摘要： A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions (160) to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric (144) becomes thick between the floating gates, weakening the control gate's (104) electrical field in the channel.
摘要翻译：存储单元（110）具有多个浮动栅极（120L，120R）。沟道区域（170）包括与相应浮动栅极相邻的多个子区域（220L，220R），以及浮置栅极之间的连接区域（210）。连接区域具有与源极/漏极区域（160）相同的导电类型以增加沟道导电性。因此，即使栅极间电介质（144）在浮置栅极之间变厚，削弱了沟道中的控制栅极（104）电场，浮动栅极也可以更靠近在一起。

43. 发明申请

US20070153175A1 Liquid crystal display device and method of fabricating the same 有权
标题翻译：液晶显示装置及其制造方法
公开(公告)号：US20070153175A1
公开(公告)日：2007-07-05
申请号：US11643499
申请日：2006-12-20
申请人： Sung-Soo Chang , Woo-Hyun Kim , Jin-Ho Kim
发明人： Sung-Soo Chang , Woo-Hyun Kim , Jin-Ho Kim
IPC分类号： G02F1/1335
CPC分类号： G02F1/133555 , G02F1/133504 , G02F1/133514
摘要： A liquid crystal display device includes an array substrate having reflective and transmissive regions in a pixel region, wherein the array substrate includes a reflective electrode corresponding to the reflective region and a pixel electrode on a first substrate. A color filter substrate defines the reflective region and the transmissive region in the pixel region. The color filter substrate includes a color filter with first and second portions that correspond to the respective transmissive and reflective regions on a second substrate. The thickness of the second portion is less than a thickness of the first portion. The combined thickness of the scatter and the thickness of the second portion is greater than the thickness of the first portion; and a liquid crystal layer between the array and color filter substrates.
摘要翻译：一种液晶显示装置，具备在像素区域具有反射和透射区域的阵列基板，其中阵列基板包括对应于反射区域的反射电极和在第一基板上的像素电极。滤色器基板限定像素区域中的反射区域和透射区域。滤色器基板包括滤色器，滤色器具有对应于第二基板上的相应透射和反射区域的第一和第二部分。第二部分的厚度小于第一部分的厚度。第二部分的散射和厚度的组合厚度大于第一部分的厚度; 以及阵列和滤色器基板之间的液晶层。

44. 发明申请

US20060292810A1 Method of manufacturing a capacitor 审中-公开
标题翻译：制造电容器的方法
公开(公告)号：US20060292810A1
公开(公告)日：2006-12-28
申请号：US11448769
申请日：2006-06-08
申请人： Jung-Hun Seo , Hyun-Young Kim , Young-Wook Park , Jin-Gi Hong , Kun-Sang Park , Jin-Ho Kim , Kyung-Bum Koo
发明人： Jung-Hun Seo , Hyun-Young Kim , Young-Wook Park , Jin-Gi Hong , Kun-Sang Park , Jin-Ho Kim , Kyung-Bum Koo
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L21/28562 , H01L27/10817 , H01L27/10852
摘要： In methods of manufacturing capacitors, a first metal compound may be deposited on a substrate using first and second source gases. The first and the second source gases may be provided onto the substrate by a first flow rate ratio in which a deposition rate of the first metal compound by surface reaction between the source gases is higher than that by mass transfer between the source gases. A second metal compound may be deposited on the first metal compound and undesired materials may be removed by providing the source gases with a second flow rate ratio different from the first flow rate ratio. Depositing the first and the second metal compounds may be repeated to form a lower electrode. A dielectric layer and an upper electrode may be formed on the lower electrode. Accordingly, permeation of an etching liquid or gas may be reduced during an etching process.
摘要翻译：在制造电容器的方法中，可以使用第一和第二源气体在基板上沉积第一金属化合物。可以通过第一流量比将第一和第二源气体提供到基底上，其中通过源气体之间的表面反应使第一金属化合物的沉积速率高于源气体之间的质量传递的沉积速率。可以将第二金属化合物沉积在第一金属化合物上，并且可以通过提供不同于第一流速比的第二流量比来提供源气体来除去不需要的物质。可以重复沉积第一和第二金属化合物以形成下电极。电介质层和上电极可以形成在下电极上。因此，在蚀刻过程中可能会减少蚀刻液体或气体的渗透。

45. 发明申请

US20050227437A1 Method of forming ONO-type sidewall with reduced bird's beak 有权
标题翻译：用鸟喙形成ONO型侧壁的方法
公开(公告)号：US20050227437A1
公开(公告)日：2005-10-13
申请号：US10821100
申请日：2004-04-07
申请人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Leung , Chia-Shun Hsiao , George Kovall , Steven Yang
发明人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Leung , Chia-Shun Hsiao , George Kovall , Steven Yang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/788
CPC分类号： H01L21/28273 , H01L29/42328 , H01L29/513 , H01L29/7881
摘要： Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.
摘要翻译：通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分材料堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。结果，氧化不沿着侧壁的多层高度均匀地进行。本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为深深地通过侧壁的已氧化层，例如氧化硅层。结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。

46. 发明授权

US06924542B2 Trench isolation without grooving 有权
公开(公告)号：US06924542B2
公开(公告)日：2005-08-02
申请号：US10901948
申请日：2004-07-29
申请人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
发明人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
IPC分类号： H01L21/762 , H01L29/00 , H01L21/8238
CPC分类号： H01L21/76229
摘要： A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

47. 发明申请

US20050054141A1 Thin semiconductor package having stackable lead frame and method of manufacturing the same 失效
标题翻译：具有可堆叠引线框的薄型半导体封装及其制造方法
公开(公告)号：US20050054141A1
公开(公告)日：2005-03-10
申请号：US10834187
申请日：2004-04-29
申请人： Jin-Ho Kim , Sung-Hwan Yoon
发明人： Jin-Ho Kim , Sung-Hwan Yoon
IPC分类号： H01L23/12 , H01L21/44 , H01L23/31 , H01L23/495 , H01L25/10
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49551 , H01L24/48 , H01L25/105 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/07802 , Y10T428/24207 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided is a thin semiconductor package comprising a semiconductor chip and a lead frame, the lead frame including a paddle portion configured for mounting the semiconductor chip in a manner that exposes bonding pads within an aperture formed in a center portion of the lead frame and a peripheral terminal pad portion for establishing external contacts. A plurality of bonding wires are used to establish electrical connection between a lower surface of the paddle part and corresponding bonding pads with intermediate leads providing connection to the terminal pad portions. The semiconductor chip, lead frame and bonding wires may then be encapsulated to form a thin semiconductor package having a thickness substantially equal to that of the terminal pad portions. The thin semiconductor packages may, in turn, be used to form multi-chip stack packages using known good semiconductor chips to form a high-density compound semiconductor packages.
摘要翻译：提供了一种薄半导体封装，其包括半导体芯片和引线框架，该引线框架包括：配置用于以形成在引线框的中心部分中的孔内露出焊盘的方式安装半导体芯片的桨形部分，端子焊盘部分，用于建立外部触点。多个接合线用于在桨形部分的下表面和相应的接合焊盘之间建立电连接，中间引线提供与端子焊盘部分的连接。然后可以将半导体芯片，引线框和接合线封装成具有基本上等于端子焊盘部分的厚度的薄的半导体封装。薄的半导体封装又可以用于使用已知的良好半导体芯片形成多芯片堆叠封装以形成高密度化合物半导体封装。

48. 发明申请

US20050045921A1 Semiconductor device having LDD-type source/drain regions and fabrication method thereof 有权
标题翻译：具有LDD型源极/漏极区域的半导体器件及其制造方法
公开(公告)号：US20050045921A1
公开(公告)日：2005-03-03
申请号：US10948883
申请日：2004-09-24
申请人： Do-Hyung Kim , Jin-Ho Kim , Byung-Jun Hwang
发明人： Do-Hyung Kim , Jin-Ho Kim , Byung-Jun Hwang
IPC分类号： H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/06
CPC分类号： H01L29/6653 , H01L21/76801 , H01L21/76832 , H01L21/76837 , H01L21/76895 , H01L21/823425 , H01L29/6659
摘要： A semiconductor device having LDD-type source/drain regions and a method of fabricating the same are provided. The semiconductor device includes at least a pair of gate patterns disposed on a semiconductor substrate and LDD-type source/drain regions disposed at both sides of the gate patterns. The substrate having the gate patterns and the LDD-type source/drain regions is covered with a conformal etch stop layer. The etch stop layer is covered with an interlayer insulating layer. The LDD-type source/drain region is exposed by a contact hole that penetrates the interlayer insulating layer and the etch stop layer. The method of forming the LDD-type source/drain regions and the etch stop layer includes forming low-concentration source/drain regions at both sides of the gate patterns and forming the conformal etch stop layer on the substrate having the low-concentration source/drain regions. Gate spacers are then formed on the sidewalls of the gate patterns. Using the gate patterns and the gate spacers as implantation masks, impurity ions are implanted into the semiconductor substrate to form high-concentration source/drain regions. The spacers are then selectively removed. An interlayer insulating layer is formed on the substrate where the spacers are removed.
摘要翻译：提供具有LDD型源极/漏极区域的半导体器件及其制造方法。半导体器件包括设置在半导体衬底上的至少一对栅极图案和设置在栅极图案两侧的LDD型源极/漏极区域。具有栅极图案和LDD型源极/漏极区域的衬底被保形蚀刻停止层覆盖。蚀刻停止层被层间绝缘层覆盖。 LDD型源极/漏极区域通过穿透层间绝缘层和蚀刻停止层的接触孔露出。形成LDD型源极/漏极区域和蚀刻停止层的方法包括在栅极图案的两侧形成低浓度源极/漏极区域，并在具有低浓度源/漏极区域的衬底上形成保形蚀刻停止层，漏区。然后在栅极图案的侧壁上形成栅极间隔物。使用栅极图案和栅极间隔物作为注入掩模，将杂质离子注入到半导体衬底中以形成高浓度源极/漏极区域。然后选择性地去除间隔物。在基板上形成层间绝缘层，其中隔离物被去除。

49. 发明申请

US20050039944A1 Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate 有权
标题翻译：用于球栅阵列（BGA）封装的非阻焊掩模型（NSMD）型布线基板及其制造方法
公开(公告)号：US20050039944A1
公开(公告)日：2005-02-24
申请号：US10850864
申请日：2004-05-21
申请人： Jin-Ho Kim , In-Ku Kang , Hee-Kook Choi
发明人： Jin-Ho Kim , In-Ku Kang , Hee-Kook Choi
IPC分类号： H01L23/48 , H05K3/24 , H05K3/34 , H05K1/09 , H05K1/02
CPC分类号： H05K3/3452 , H01L2224/10 , H05K3/243 , H05K2201/0989 , H05K2201/10734 , H05K2203/0577 , H05K2203/058
摘要： In one embodiment, a pad is formed on a substrate surface. The pad is connected with a connecting pattern. A first mask is formed on the substrate. The first mask has a first opening exposing at least a portion of the pad and a portion of the connecting pattern. A second mask is formed on the first mask. The second mask has a second opening exposing at least a portion of the pad and a portion of the connecting pattern. A boundary surface or sidewall of the first opening is not coplanar with a boundary surface or sidewall of the second opening. Therefore, stresses may be prevented from concentrating on the boundary surface of the first opening, thereby allowing dispersion of the stresses and restraining pattern cracks.
摘要翻译：在一个实施例中，衬垫形成在衬底表面上。垫与连接图案连接。在基板上形成第一掩模。第一掩模具有暴露焊盘的至少一部分和连接图案的一部分的第一开口。在第一掩模上形成第二掩模。第二掩模具有暴露焊盘的至少一部分和连接图案的一部分的第二开口。第一开口的边界面或侧壁不与第二开口的边界面或侧壁共面。因此，可以防止应力集中在第一开口的边界面上，从而允许应力分散和约束图案裂纹。

50. 发明授权

US09230500B2 Expanded 3D stereoscopic display system 有权
标题翻译：扩展3D立体显示系统
公开(公告)号：US09230500B2
公开(公告)日：2016-01-05
申请号：US13565421
申请日：2012-08-02
申请人： Ung-Yeon Yang , Hye-Mi Kim , Jin-Ho Kim , Ki-Hong Kim , Gil-Haeng Lee
发明人： Ung-Yeon Yang , Hye-Mi Kim , Jin-Ho Kim , Ki-Hong Kim , Gil-Haeng Lee
IPC分类号： H04N13/02 , G09G5/00 , H04N13/00 , H04N13/04
CPC分类号： G09G5/00 , H04N13/161 , H04N13/243 , H04N13/363 , H04N13/383
摘要： An expanded three-dimensional (3D) stereoscopic image display system is provided. The expanded 3D stereoscopic image display system according to an embodiment of the present invention provides a display platform that presents integrated services by fusing homogeneous and heterogeneous display devices in a single space, and an operation technique of the display platform.
摘要翻译：提供了一种扩展的立体（3D）立体图像显示系统。根据本发明的实施例的扩展的3D立体图像显示系统提供了通过在单个空间中融合均匀和异质显示设备来呈现综合服务的显示平台以及显示平台的操作技术。

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