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41. 发明授权

US07122425B2 Methods of forming semiconductor constructions 有权
公开(公告)号：US07122425B2
公开(公告)日：2006-10-17
申请号：US10925789
申请日：2004-08-24
申请人： Randal W. Chance , Gordon A. Haller , Sanh D. Tang , Steven D. Cummings
发明人： Randal W. Chance , Gordon A. Haller , Sanh D. Tang , Steven D. Cummings
IPC分类号： H01L21/8242
CPC分类号： H01L29/66666 , H01L21/823437 , H01L21/823487 , H01L27/10808 , H01L27/10876 , H01L29/42368 , H01L29/512 , H01L29/7827
摘要： The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.

42. 发明授权

US08120101B2 Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors 有权
标题翻译：半导体结构和晶体管，以及形成半导体结构和晶体管的方法
公开(公告)号：US08120101B2
公开(公告)日：2012-02-21
申请号：US12891407
申请日：2010-09-27
申请人： Sanh D. Tang , Gordon A. Haller , Kris K. Brown , Tuman Earl Allen, III
发明人： Sanh D. Tang , Gordon A. Haller , Kris K. Brown , Tuman Earl Allen, III
IPC分类号： H01L29/76
CPC分类号： H01L29/41758 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/78
摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
摘要翻译：本发明包括具有上表面的半导体衬底的晶体管器件。一对源极/漏极区域形成在半导体衬底内，并且沟道区形成在半导体衬底内并相对于半导体衬底的上表面大致垂直地延伸。栅极形成在半导体衬底中的一对源/漏区之间。

43. 发明申请

US20110169086A1 Methods of Forming Field Effect Transistors, Pluralities of Field Effect Transistors, and DRAM Circuitry Comprising a Plurality of Individual Memory Cells 有权
标题翻译：形成场效应晶体管的方法，多个场效应晶体管和包含多个存储单元的DRAM电路
公开(公告)号：US20110169086A1
公开(公告)日：2011-07-14
申请号：US13070256
申请日：2011-03-23
申请人： Paul Grisham , Gordon A. Haller , Sanh D. Tang
发明人： Paul Grisham , Gordon A. Haller , Sanh D. Tang
IPC分类号： H01L29/772 , H01L21/762
CPC分类号： H01L29/7851 , H01L21/76232 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66818 , H01L29/7854
摘要： A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底内形成沟槽隔离材料，并在沟道区的长度上在半导体材料沟道区的相对侧上形成沟道隔离材料。沟槽隔离材料形成为包括沿着沟道长度部分地在沟道区域下方朝向彼此延伸的相对的绝缘突起，并且半导体材料被接收在突起上。蚀刻沟槽隔离材料以沿着沟道长度露出半导体材料的相对侧。半导体材料的暴露的相对侧沿通道长度被蚀刻以形成相对于突出部向上突出的通道翅片。栅极沿着沟道长度形成在鳍的顶部和相对侧上。公开了其它方法和结构。

44. 发明授权

US07939403B2 Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells 有权
标题翻译：形成场效应晶体管，多个场效应晶体管和包括多个单独存储单元的DRAM电路的方法
公开(公告)号：US07939403B2
公开(公告)日：2011-05-10
申请号：US11601478
申请日：2006-11-17
申请人： Paul Grisham , Gordon A. Haller , Sanh D. Tang
发明人： Paul Grisham , Gordon A. Haller , Sanh D. Tang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7851 , H01L21/76232 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66818 , H01L29/7854
摘要： A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底内形成沟槽隔离材料，并在沟道区的长度上在半导体材料沟道区的相对侧上形成沟道隔离材料。沟槽隔离材料形成为包括沿着沟道长度部分地在沟道区域下方朝向彼此延伸的相对的绝缘突起，并且半导体材料被接收在突起上。蚀刻沟槽隔离材料以沿着沟道长度露出半导体材料的相对侧。半导体材料的暴露的相对侧沿通道长度被蚀刻以形成相对于突出部向上突出的通道翅片。栅极沿着沟道长度形成在鳍的顶部和相对侧上。公开了其它方法和结构。

45. 发明授权

US07935999B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07935999B2
公开(公告)日：2011-05-03
申请号：US12710082
申请日：2010-02-22
申请人： Gordon A. Haller , David K. Hwang , Sanh Dang Tang , Ceredig Roberts
发明人： Gordon A. Haller , David K. Hwang , Sanh Dang Tang , Ceredig Roberts
IPC分类号： H01L21/8242
CPC分类号： H01L21/3088 , H01L21/0338 , H01L27/0207 , H01L27/10891 , H01L27/10894
摘要： A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.
摘要翻译：存储器件包括有源区域，其包括源极和限定第一轴线的至少两个漏极。至少两个基本上平行的字线由第一间距限定，一个字线位于每个漏极和源之间。数字线由第二间距限定，其中一个数字线耦合到源并形成第二轴。存储器阵列的有效区域与由字线和数字线限定的栅格倾斜45°。字线间距约为1.5F，而数字线间距约为3F。

46. 发明授权

US07772632B2 Memory arrays and methods of fabricating memory arrays 有权
标题翻译：存储器阵列和制造存储器阵列的方法
公开(公告)号：US07772632B2
公开(公告)日：2010-08-10
申请号：US11507696
申请日：2006-08-21
申请人： Gordon A. Haller , Sanh D. Tang
发明人： Gordon A. Haller , Sanh D. Tang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/66621 , G11C11/405 , H01L27/10823 , H01L27/10844 , H01L27/10876 , H01L27/10891
摘要： A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.
摘要翻译：存储器阵列包括形成在半导体衬底上的多个存储单元。存储单元的个体包括分别包括栅极，沟道区和一对源极/漏极区的第一和第二场效应晶体管。第一和第二场效应晶体管的栅极被硬连线在一起。导电数据线硬连接到两个源极/漏极区域。电荷存储装置硬连接到除二者之外的源极/漏极区域中的至少一个。考虑了其他方面和实现方式，包括制造存储器阵列的方法。

47. 发明申请

US20100148249A1 Method Of Manufacturing A Memory Device 有权
标题翻译：一种存储器件的制造方法
公开(公告)号：US20100148249A1
公开(公告)日：2010-06-17
申请号：US12710082
申请日：2010-02-22
申请人： Gordon A. Haller , David K. Hwang , Sanh Dang Tang , Ceredig Roberts
发明人： Gordon A. Haller , David K. Hwang , Sanh Dang Tang , Ceredig Roberts
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/3088 , H01L21/0338 , H01L27/0207 , H01L27/10891 , H01L27/10894
摘要： A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.
摘要翻译：存储器件包括有源区域，其包括源极和限定第一轴线的至少两个漏极。至少两个基本上平行的字线由第一间距限定，一个字线位于每个漏极和源之间。数字线由第二间距限定，其中一个数字线耦合到源并形成第二轴。存储器阵列的有效区域与由字线和数字线限定的栅格倾斜45°。字线间距约为1.5F，而数字线间距约为3F。

48. 发明授权

US07589369B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07589369B2
公开(公告)日：2009-09-15
申请号：US12221178
申请日：2008-07-30
申请人： Gordon A. Haller
发明人： Gordon A. Haller
IPC分类号： H01L27/108
CPC分类号： H01L21/823468 , H01L21/823418 , H01L27/1052 , H01L27/10808 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/4236
摘要： The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors sharing a source/drain region corresponding to a bitline contact location, and having other source/drain regions corresponding to capacitor contact locations. A peripheral transistor gate is formed over the peripheral region. Electrically insulative material is formed over the peripheral transistor gate, and also over the bitline contact location. The insulative material is patterned to form sidewall spacers along sidewalls of the peripheral transistor gate, and to form a protective block over the bitline contact location. Subsequently, capacitors are formed which extend over the protective block, and which electrically connect with the capacitor contact locations. The invention also includes semiconductor constructions.
摘要翻译：本发明包括一种方法，其中半导体衬底被设置为具有存储器阵列区域和外围区域在存储器阵列区域的外部。成对的晶体管形成在存储器阵列区域内，这些成对的晶体管共享与位线接触位置对应的源极/漏极区域，并且具有与电容器接触位置对应的其它源极/漏极区域。外围晶体管栅极形成在周边区域上。电绝缘材料形成在外围晶体管栅极上，并且也位于位线接触位置之上。将绝缘材料图案化以形成沿着外围晶体管栅极的侧壁的侧壁间隔，并且在位线接触位置上形成保护块。随后，形成了在保护块上延伸并与电容器接触位置电连接的电容器。本发明还包括半导体结构。

49. 发明申请

US20080119020A1 Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells 有权
标题翻译：形成场效应晶体管，多个场效应晶体管和包括多个单独存储单元的DRAM电路的方法
公开(公告)号：US20080119020A1
公开(公告)日：2008-05-22
申请号：US11601478
申请日：2006-11-17
申请人： Paul Grisham , Gordon A. Haller , Sanh D. Tang
发明人： Paul Grisham , Gordon A. Haller , Sanh D. Tang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7851 , H01L21/76232 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66818 , H01L29/7854
摘要： A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底内形成沟槽隔离材料，并在沟道区的长度上在半导体材料沟道区的相对侧上形成沟道隔离材料。沟槽隔离材料形成为包括沿着沟道长度部分地在沟道区域下方朝向彼此延伸的相对的绝缘突起，并且半导体材料被接收在突起上。蚀刻沟槽隔离材料以沿着沟道长度露出半导体材料的相对侧。半导体材料的暴露的相对侧沿通道长度被蚀刻以形成相对于突出部向上突出的通道翅片。栅极沿着沟道长度形成在鳍的顶部和相对侧上。公开了其它方法和结构。

50. 发明申请

US20080064154A1 Process flow for metal gate access device 有权
标题翻译：金属栅极接入装置的工艺流程
公开(公告)号：US20080064154A1
公开(公告)日：2008-03-13
申请号：US11521329
申请日：2006-09-13
申请人： Gordon A. Haller , Sanh D. Tang
发明人： Gordon A. Haller , Sanh D. Tang
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823437 , H01L21/823412 , H01L27/10823 , H01L27/10826 , H01L27/10844 , H01L29/785
摘要： Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an access device following formation of the periphery transistor gates. Access devices and systems including same are also disclosed.
摘要翻译：集成电路器件中栅极晶体管的制造方法能够形成具有P型工作功能的凹陷接入器件结构或FinFET结构。制造方法还提供了在形成周边晶体管栅极之后形成存取器件的存取晶体管栅极。还公开了包括它们的接入设备和系统。

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