专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JPH06223179A METHOD AND DEVICE FOR DECIDING WHETHER OR NOT THERE IS SPECIFIC OBJECT IN COLOR IMAGE AND COLOR MOVING PICTURE CUT RETRIEVAL DISPLAY SYSTEM USING THE DEVICE 失效
公开(公告)号：JPH06223179A
公开(公告)日：1994-08-12
申请号：JP26103392
申请日：1992-09-30
申请人： HITACHI LTD
发明人： NAGASAKA AKIO , UEDA HIROTADA
IPC分类号： G06F3/14 , G06F3/048 , G06T7/00 , G06T7/20 , H04N9/64 , H04N9/79 , G06F15/70
摘要： PURPOSE:To improve the reliability and performance of technology regarding color moving picture detection by preventing an omission of detection of a frame containing an object from a color moving picture. CONSTITUTION:Plural partial areas of similar colors are extracted as color groups from the color image of the specific object and a couple of adjacent color groups showing the feature of the specific object are selected among the extracted color groups; when more than a specific number of the couples of color groups are included in an optional color image, it is decided that the specific object is included in the optional color image, thus deciding whether or not the specific object is present in the color image.

42. 发明专利

JPH0574969B2 失效
公开(公告)号：JPH0574969B2
公开(公告)日：1993-10-19
申请号：JP23315284
申请日：1984-11-07
申请人： HITACHI LTD
发明人： NAKAGAWA TETSUYA , KANEKO KENJI , HAGIWARA YOSHIMUNE , MATSUSHIMA HITOSHI , UEDA HIROTADA
IPC分类号： H03K19/20 , G06F7/501 , G06F7/53 , H03K19/0948 , G06F7/50

43. 发明专利

JPH01166221A INFORMATION PROCESSOR 失效
公开(公告)号：JPH01166221A
公开(公告)日：1989-06-30
申请号：JP32411287
申请日：1987-12-23
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , KANEKO KENJI , NAKAGAWA TETSUYA , UEDA HIROTADA , HAGIWARA YOSHIMUNE
IPC分类号： G06F9/22 , G06F9/28 , G06F9/30 , G06F9/38
摘要： PURPOSE:To improve information processing ability by dividing all control functions into those having the long periods of executing time and others having the short periods respectively and validating the field where the control functions of long periods are described at every other fixed interval of a program address space. CONSTITUTION:An instruction code 201 is divided into a 1st field 202 and a 2nd field 203. The control functions having the short period of executing time are described in the field 202 together with the control functions having the long periods described in the field 203 respectively. Thus the instruction executing intervals are different from each other at every field and therefore the address signals 112 and 113 supplied to address decoders 103 and 104 respectively have different types from each other. Furthermore the instruction codes 116 and 117 have different types of instruction executing timing for separate production of timing signals 115 and 114 respectively. In such a way, the executing speeds can be set at every field and therefore the overall processing speed is increased even with a parallel working processor having a long horizontal instruction code.

44. 发明专利

JPH01131971A METHOD AND DEVICE FOR PROCESSING AFFINE TRANSFORMATION OF IMAGE 失效
公开(公告)号：JPH01131971A
公开(公告)日：1989-05-24
申请号：JP28931887
申请日：1987-11-18
申请人： HITACHI LTD
发明人： UEDA HIROTADA , MATSUSHIMA HITOSHI
IPC分类号： G06T3/00
摘要： PURPOSE:To perform the affine transformation of a binary image at almost the same processing speed only by a small memory circuit and a simple transformation circuit or a program by combining rotation at 90 deg., expansion and compression only in a direction of (y)-axis, and the transformation of an oblique axis only in a direction of (x)-axis. CONSTITUTION:An original image stored in an image memory 30 is read out in sequence of raster scan by an oblique axis transformation circuit 10, and receives the transformation of the oblique axis in the direction of (x)-axis and the transformation of the expansion and compression in the direction of (y)-axis, then, is returned to a memory 30. Next, the image is read out by a 90 deg. rotation circuit 20, and the rotation at 90 deg. is applied, then, it is returned to the memory 30 again. And finally, the same transformation as the previous one is applied by the oblique axis transformation circuit 10 again, and a final image is generated in the image memory 30. In such a way, the binary image is stored in the memory with ordinary word constitution, and the rotation or the affine transformation of the image can be performed without complicating a circuit.

45. 发明专利

JPS6329874A CONTROLLING METHOD FOR MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPS6329874A
公开(公告)日：1988-02-08
申请号：JP17154186
申请日：1986-07-23
申请人： HITACHI LTD
发明人： UEDA HIROTADA , KATO KANJI , MATSUSHIMA HITOSHI
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80 , G06T1/00 , G06T1/20 , G06T5/20
摘要： PURPOSE:To speed up the exchange of data between processors and to improve the processing speed of a multiprocessor by reducing the number of transfer directions at the time of transmitting/receiving the image data between the processors. CONSTITUTION:Partial images 101-103 exist at the periphery of a partial image 100. The picture element of a processed result is written in an upper left corner position of a mask area 303 and an abnormal part 104 is previously overlapped to the peripheral three partial images 101-103. Correct processing can be attained by replacing the abnormal part 104 of the partial image 100 by the normal parts 105-109 of the peripheral partial images. Consequently, data transfer to the processors corresponding to respective partial images can be restricted only to three directions and the data transfer can be speeded up.

46. 发明专利

JPS62208158A MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPS62208158A
公开(公告)日：1987-09-12
申请号：JP5123686
申请日：1986-03-08
申请人： HITACHI LTD
发明人： UEDA HIROTADA , KATO KANJI , MATSUSHIMA HITOSHI
IPC分类号： G06F15/173 , G06F13/16 , G06F15/80 , G06T1/00 , G06T1/20
摘要： PURPOSE:To increase processing speed and to provide the titled system with diversity by connecting bus control circuits like shift registers between respective processor components and processor devices consisting of local memories to form a ring bus. CONSTITUTION:The bus control circuit 4 is provided between respective processor components 3 and local memories 2 and plural bus control circuit are connected like shift registers. The shift registers from the ring bus 1 and are controlled by a ring bus control circuit 8. The whole system is controlled by a microcomputer 5 and connected to a host computer through a system bus 10 and an interface part 9 for I/O. The ring bus 1 can be used for executing the I/O of an image from/to an external equipments at high speed and can attain may operation modes.

47. 发明专利

JPS62159267A ALLOCATING SYSTEM FOR DEVICE NUMBER 失效
公开(公告)号：JPS62159267A
公开(公告)日：1987-07-15
申请号：JP55586
申请日：1986-01-08
申请人： HITACHI LTD
发明人： KATO KANJI , UEDA HIROTADA , MATSUSHIMA HITOSHI
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To attain the second dynamic allocation of device numbers by adding a device number identifying circuit into a processor. CONSTITUTION:When the reset signal 60 is outputted from a controller 10, the processors 1-N are all set at input/output invalid signals. The processors containing the input/output invalid signals inputted to the input/output controller inputs IOMSKi2-in are inhibited for the input/output actions to the control signal given from a controller 10. Thus only a processor 1 containing the inverse signal inputted to the input/output control signal input IOMSKi1 from an inverter 500 can perform the input/output actions is response to the control signal of the controller 10. Here a specific number is set to a device number identifying circuit provided into each of processors 1-N. Thus it is possible to allocate again the device number of the processor 1.

48. 发明专利

JPS61112429A Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：JPS61112429A
公开(公告)日：1986-05-30
申请号：JP23315284
申请日：1984-11-07
申请人： Hitachi Ltd
发明人： NAKAGAWA TETSUYA , KANEKO KENJI , HAGIWARA YOSHIMUNE , MATSUSHIMA HITOSHI , UEDA HIROTADA
IPC分类号： H03K19/20 , G06F7/501 , G06F7/53 , H03K19/0948
CPC分类号： H03K19/0948
摘要： PURPOSE:To realize an optional logical equation with one kind of cell and inverter by using a logical gate having four inputs and whose output shown H,L levels and high impedance depending on the combination of the inputs. CONSTITUTION:The midpoint X of CMOS FETs (M13, M14, M29, M30) and CMOS FET of the same polarity (M15, M16, M31, M32) is connected mutually. In this circuit connection tri-state (H, L levels and high impedance) is obtained by two input signals. Since an optional logic such as AND or OR is obtained depending on the combination of inputs, a full adder is constituted and the power consumption is reduced because of the adoption of CMOS.
摘要翻译：目的：通过使用具有四个输入的逻辑门，根据输入的组合，其输出显示H，L电平和高阻抗，实现一种单元和反相器的可选逻辑方程。构成：相互极性连接的CMOS FET（M13，M14，M29，M30）和CMOS FET的中点X相互连接。（M15，M16，M31，M32）相互连接。在该电路中，通过两个输入信号获得三态（H，L电平和高阻抗）。由于根据输入的组合获得诸如AND或OR的可选逻辑，所以构成了全加器，并且由于采用了CMOS而降低了功耗。

49. 发明专利

JPS6058505B2 失效
公开(公告)号：JPS6058505B2
公开(公告)日：1985-12-20
申请号：JP4032278
申请日：1978-04-07
申请人： HITACHI LTD
发明人： UEDA HIROTADA , YASUE RIICHI , KARASUNO TAKESHI
IPC分类号： G06K7/00 , G06K7/10 , G06K7/12

50. 发明专利

JPS60157672A PICTURE PROCESSING CIRCUIT 失效
公开(公告)号：JPS60157672A
公开(公告)日：1985-08-17
申请号：JP1192484
申请日：1984-01-27
申请人： HITACHI LTD
发明人： UEDA HIROTADA , SUZUKI RIYUUICHI , KATOU KANJI , KASHIOKA SEIJI , NAGAI HARUO
IPC分类号： G06T7/00 , G06T1/20 , G06T7/60
摘要： PURPOSE:To obtain a multi-functional picture processing circuit by properly attaching several arithmetic circuits and input switch circuits to a structure requiring a density value frequency distribution. CONSTITUTION:A selector A44 has functions of using an input 56 of one of arithmetic parts 411 and 412 as picture data 57 and as a picture address 58 and is controlled by a select signal A59. While a selector B45 has functions of using an address 58 as well as an outer address 61, and is controlled by a select signal 62. A read/write control circuit 43, as in clearing the contents in a memory 42 by a select signal B62, has a function of switching to add an outer write pulse 65 to a memory 42, when necessary.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式