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41. 发明专利

JPS62154980A SOLID-STATE IMAGE PICKUP DEVICE 失效
公开(公告)号：JPS62154980A
公开(公告)日：1987-07-09
申请号：JP29262685
申请日：1985-12-27
申请人： HITACHI LTD
发明人： SASAKI TOSHIO , AOKI MASAKAZU , MASUHARA TOSHIAKI , HORIGUCHI SHINJI , NAKAGOME YOSHINOBU
IPC分类号： H01L27/146 , H01L27/14 , H04N5/335 , H04N5/341 , H04N5/355 , H04N5/357 , H04N5/374 , H04N5/378
摘要： PURPOSE:To shorten an A/D conversion time by providing an A/D converting mechanism for each column of a vertical signal readout pat and processing light image signals in parallel. CONSTITUTION:A charge packet only carries quinary digital information on presence (ON) or absence (OFF) after a signal is outputted from a photocell 100, and then multi-value level information carries effectively timing data t1-t5 given by pulses from a temporary storage part 134 and a reference pulse generator 135 which controls a row selection applying pulse phiw. Therefore, signal voltages on vertical signal lines 104 and 106 do not require high-accuracy analog amplification like normal A/D conversion. Consequently, a large-scale and large- power circuit is not required like a conventional A/D converting circuit and A/D converting mechanism are easily provided on a chip, thereby reducing the size of the system.

42. 发明专利

JPS6196586A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：JPS6196586A
公开(公告)日：1986-05-15
申请号：JP21617084
申请日：1984-10-17
申请人： Hitachi Ltd
发明人： YAMAMOTO AKIRA , SAEKI AKIRA , MINATO OSAMU , SASAKI TOSHIO , SASAKI KATSURO
IPC分类号： G11C7/00 , G11C11/34 , H01L27/10
摘要： PURPOSE: To execute low power consumption by installing a word line for plural memory cells each of which stores plural pieces of bit information, and linking this and a block selecting line by the gate circuit controlled by a data line selecting signal.
CONSTITUTION: The linking of large word lines W0, W1... of the block selecting line operating in response to an X address decoder output and word lines WD0, WD1... for eight memory cells MC0WMC7 each which stores bit information, etc., is selectively controlled through FETQ3, Q4... operating in response to selecting signals DS0, DS1... of the data line selected by a Y address decoder output. By such constitution, a wasteful electric current will not flow at the memory cell in which the data line is in a non-selective condition, and the low power consumption can be attained.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过为存储多条位信息的多个存储单元安装字线来执行低功耗，并通过由数据线选择信号控制的门电路将其与块选择线进行链接。构成：响应于X地址解码器输出操作的块选择线的大字线W0，W1 ...与存储位信息的八个存储单元MC0-MC7的字线WD0，WD1 ...的链接，通过FETQ3，Q4 ...选择性地控制，响应于由Y地址解码器输出选择的数据线的选择信号DS0，DS1 ...而工作。通过这种结构，在数据线处于非选择状态的存储单元处不会流入浪费电流，能够实现低功耗。

43. 发明专利

JPS6134968A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6134968A
公开(公告)日：1986-02-19
申请号：JP9360885
申请日：1985-05-02
申请人： Hitachi Ltd
发明人： SAKAI YOSHIO , MASUHARA TOSHIAKI , HATA OSAMU , SASAKI TOSHIO
IPC分类号： G11C11/413 , H01L21/8244 , H01L27/10 , H01L27/11
CPC分类号： H01L27/11
摘要： PURPOSE:To innovate in the design of the structure of a static-type MOS memory cell capable of higher integration by a method wherein a semiconductor substrate is used as a power line for the supply of a micro-current to make up for a leak from the MOS transistor. CONSTITUTION:A high-resistance polycrystalline silicon layer 29 for the supply of a micro-current is formed on an SiO2 film 27 in contact with an end of a drain 24. An end of the silicon layer 29 is connected to the drain 24 with the intermediary of an N type polycrystalline silicon layer 30 and the other end thereof is provided with an N type polycrystalline silicon layer 31. The N type polycrystalline silicon layer 31 is connected through a window provided in the SiO2 film 27 to an N type region 33 provided in the surface in the surface portion of an opening 32 reaching the surface of an N type silicon substrate 21 formed on a part of a P type region 22. Accordingly, the micro-current to make up a leak in a MOS transistor flows from the N type silicon substrate 21 biased with a power source voltage to the MOS transistor drain region 24 through the high-resistance polycrystalline silicon layer 29.
摘要翻译：目的：通过采用半导体衬底作为供电微电流的电源线来弥补泄漏的方法，能够实现更高集成度的静态型MOS存储单元的结构设计。 MOS晶体管。构成：在与漏极24的一端接触的SiO2膜27上形成用于供给微电流的高电阻多晶硅层29.硅层29的一端与漏极24连接， N +型多晶硅层30的中间体，其另一端设置有N +型多晶硅层31.N +型多晶硅层31通过设置在SiO2中的窗口连接膜27与设置在开口32的表面部分中的形成在P型区域22的一部分上的N型硅基板21的表面的表面中的N +型区域33.因此，微电流为了弥补MOS晶体管的漏电流，通过高电阻多晶硅层29从偏置有电源电压的N型硅衬底21流向MOS晶体管漏区24。

44. 发明专利

JPS60140854A HIGH-RESISTANT ELEMENT 失效
公开(公告)号：JPS60140854A
公开(公告)日：1985-07-25
申请号：JP24629283
申请日：1983-12-28
申请人： HITACHI LTD
发明人： SAKAI YOSHIO , YAMANAKA TOSHIAKI , NAGAI AKIRA , YAMAMOTO SHIYUUICHI , HAYASHIDA TETSUYA , KAWAMOTO YOSHIFUMI , KURE TOKUO , MINATO OSAMU , SASAKI TOSHIO
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PURPOSE:To obtain the titled element of stable electric characteristics with a small required area by a method wherein a high-resistant polycrystalline Si element is vertically formed on the side wall of a deep hole of a semiconductor substrate via insulation film, and power is supplied to the high-resistant element from the substrate by contacting the element with the substrate at the bottom of the hole. CONSTITUTION:A P type well region 10 is formed on the surface of the N type Si substrate 9, and a high-concentration N type region 11 serving as the drain region is formed. The deep hole 12 reaching the substrate 9 is formed, and the insulation film 13 is formed on the side wall of the deep hole, which side wall is coated with high-resistant polycrystalline Si 14. The bottom of the Si 14 is in contact with the substrate 9, and therefore power can be supplied to the Si 14 from the substrate 9. Besides, an N type high-concentration region 15 formed above the Si 14 is connected to the drain region 11 with a wiring 16; thus, micro currents are supplied from the substrate 9 to the drain region 11, and the static action of a memory cell is enabled.

45. 发明专利

JPS60767A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60767A
公开(公告)日：1985-01-05
申请号：JP10767883
申请日：1983-06-17
申请人： HITACHI LTD
发明人： MINATO OSAMU , SASAKI TOSHIO , MASUHARA TOSHIAKI
IPC分类号： H01L29/78 , H01L27/02 , H01L27/06 , H01L27/08
摘要： PURPOSE:To improve the value of a gate breakdown voltage in view from an input terminal by reducing the breakdown voltage of an MOS transistor constituting a protection device, and reducing the ON-resistance after breakdown. CONSTITUTION:An N-channel MOS transistor Tr45 is formed in a P type well 36 provided on an N type substrate 37, and an MOS Tr43 constituting the protection device in a Ptype well 50, respectively. Here, unlike the well 36, the well 50 has impurity concentration increased by a factor of 5-10, and layer resistance reduced. This construction causes the decrease in the breakdown voltage of the MOS Tr43 and the reduction of internal resistance.

46. 发明专利

JPS5818794B2 失效
公开(公告)号：JPS5818794B2
公开(公告)日：1983-04-14
申请号：JP15119180
申请日：1980-10-28
申请人： HITACHI LTD
发明人： MYOSHI TETSUO , ISHIDA MASAKATSU , SASAKI TOSHIO , WATANABE YUTAKA
IPC分类号： H05K3/22 , H05K1/02

47. 发明专利

JPS5848960A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5848960A
公开(公告)日：1983-03-23
申请号：JP15272982
申请日：1982-09-03
申请人： HITACHI LTD
发明人： MASUHARA TOSHIAKI , MINATO OSAMU , SASAKI TOSHIO , SAKAI YOSHIO , UCHIBORI KIYOBUMI , YASUI NORIMASA
IPC分类号： H01L27/08 , H01L27/092 , H01L29/78
摘要： PURPOSE:To prevent latch-up by forming a P type well biassed to ground potential to a semiconductor surface between a circuit connected to an input or output terminal and an internal circuit in a C-MOS.IC in which a PMOS transistor is shaped to an N type substrate and an NMOS transistor into the P type well formed into the substrate. CONSTITUTION:A polycrystal Si gate 17, a P drain region 16 and a P type source region 15 are formed to the N type Si substrate 5 and used as the PMOS transistor, a polycrystal Si gate 19, an N type drain region 18 and an N type source region 20 are shaped into the P type well 6 molded to the substrate 5 and employed as the NMOS transistor, and the C-MOS internal circuit is formed by these transistors. Likewise, an Si gate 11, an N type drain 10 and a source 12 are shaped into the P type well 7 and used as the NMOS transistor, a P type base extracting region 13 and an N type emitter region 14 are formed into the P type well 8, and a bipolar output circuit is formed. These wells 7, 6 are zero-biassed by P type regions 9, 21 shaped to the wells 7, 6.

48. 发明专利

JPS5810863B2 失效
公开(公告)号：JPS5810863B2
公开(公告)日：1983-02-28
申请号：JP4777978
申请日：1978-04-24
申请人： HITACHI LTD
发明人： SAKAI YOSHIO , MASUHARA TOSHIAKI , MINATO OSAMU , SASAKI TOSHIO , KATSUTO HISAO , HASHIMOTO TETSUKAZU , MURAMATSU SHINICHI , TOMOSAWA AKIHIRO
IPC分类号： G11C11/412 , H01L21/02 , H01L21/318 , H01L21/822 , H01L27/04 , H01L27/06 , H01L27/11 , H01L29/06 , H01L29/40 , H01L29/41

49. 发明专利

JPS589514B2 失效
公开(公告)号：JPS589514B2
公开(公告)日：1983-02-21
申请号：JP18702981
申请日：1981-11-24
申请人： HITACHI LTD
发明人： MASUHARA TOSHIAKI , MINATO OSAMU , SASAKI TOSHIO , KUBO SEIJI
IPC分类号： G11C11/41 , G11C7/10 , G11C11/417

50. 发明专利

JPS57162454A EQUIPMENT OF TERMINAL OF HYBRID MODULE 失效
公开(公告)号：JPS57162454A
公开(公告)日：1982-10-06
申请号：JP4753181
申请日：1981-03-31
申请人： HITACHI LTD
发明人： SANADA SAKAE , OOSAWA YOSHIYUKI , SASAKI TOSHIO , ISHIDA MASAKATSU
IPC分类号： H01L23/50 , H01L23/538
摘要： PURPOSE:To prevent generation of a crack in a substrate of hybrid module by a method wherein the diameter of a terminal pad and quantity of solder material are prescribed, and thickness of the solder material on the terminal pad is held at about 0.04mm. or less on the average, or the terminal pad is fixed to the substrate interposing an insulating layer between them. CONSTITUTION:A crack is generated because the solder material draws the substrate according to the difference of thermal expansion to be generated when they are cooled after welding is finished. When average thickness of the solder materisl on the terminal pad is held at 0.04mm. or less considering the diameter of terminal pad, quantity of the solder material, volume of gap inside of a through hole, volume of the terminal, etc., the crack is not generated in the substrate. When unevenness of thickness of substrate, the diameter of pad are considered, the larger the diameter of pad becomes, the easier thickness of the solder material can be controlled. And when the area A of substrate at the pad part/the area B of solder at the outside circumferential part is held at 6 or more, no crack is generated. At the case when short-circuit between the terminal pad 8 and the adjoining pattern 10 is generated by enlargement of the diameter of terminal pad, the terminal pad 3 is provided interposing an insulating layer 9 between the substrate, and at the case when the pad is to be provided by butt welding, no crack is generated in the substrate 1 by changing the shape of the terminal 2 and prescribing the solder material 5.

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